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IMEC (Leuven, Belgium) has announced significant progress with its 3D-SIC (3D stacked IC) technology. IMEC recently demonstrated the first functional 3D integrated circuits obtained by die-to-die stacking using 5μm Cu through-silicon vias (TSV). The 3D stacked integrated circuits will be further developed on 200mm and 300mm wafers, integrating test circuits from participating partners. The dies were realized on 200mm wafers in IMEC's reference 0.13μm CMOS process with an added Cu-TSVs process. For stacking, the top die was thinned down to 25μm and bonded to the landing die by Cu-Cu thermocompression.

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This article first appeared in the March, 2009 issue of Embedded Technology Magazine.

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