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Figure 3. The Backplane Profile Chart tells us which OpenVPX Slot Profile(s) is used, the pitch, and data rate of the backplane.
The Slot Profile that is referenced in Figure 2 gives us some details on the card plugging into the slot. For example, the slot profile number SLT6 says it’s a 6U slot profile (a 6U board), the PER says it’s a peripheral slot, 4F means it has 4 fat pipes and the 10.3.1 is where you can find details on this slot profile in the VITA 65 specification. For OpenVPX, fat pipes have 4 links (4 Tx pairs + 4 Rx pairs), thin pipes have 2 links, and ultra thin pipes have one link. The wider bands, like fat pipes, are typically used in the data plane, while the control plane will often have the thin pipe or ultra thin-pipe signals. Slot types are comprised of peripheral slots, payload slots, switch slots, or bridge slots.

The backplane profile of the backplane also provides more information. For example, this 6U 5-slot’s profile is BKP6-DIS05-11.2.16-1. The BKP6 tells us it’s a 6U backplane profile. DIS05 means it’s a distributed (like a mesh or ring) architecture and has 5 slots. The 11.2.16 is the section of the specification where you can find details on this backplane profile. The “-1” tells us the data rate is 3.125 Gbps (-2 means 5 Gbps and -3 means 6.250 Gbps).

The backplane profile chart in Figure 3 shows the profile name, the pitch, the corresponding slot profile for the backplane, the control plane data rate (if applicable) and the data rate of the backplane.

The slot type (like DIS05) section of the profile name is an important part of the description. The main fabric topologies are CEN for centralized, DIS for distributed, and HYB for hybrid. “Centralized” means it has a centralized switch slot and the routing could be similar to a Star topology. The DIS and CEN configurations typically have payload and switch slot types. The HYB will typically also define peripheral, bridge, and bus slot types like “VME” to account for connections to the legacy bus slots. The bridge slot does not mean an active bridge board (like a cPCI Bridge) is being used. Rather, it just refers to the fact that this VPX slot also has pinouts defined for the parallel bus (like VME).

Future Designs for VPX/OpenVPX

There are some interesting configurations coming up in OpenVPX. They include special connections for optical connectors and another version for a RF connector interface. VITA 67 is underway to add RF connectors to the OpenVPX backplanes. Figure 4 shows the new gold connectors on a backplane.

Another very compelling new solution for VPX is cabling systems. Compliant to the latest VITA 46 specifications, the cabling system can be used for IO to bulkhead connectors, slot-to-slot connections, and out-of-band communication. The cabling system can also be used for system development. Figure 4 also shows an example of these cables plugged into a VPX backplane. The direct cabling system also has front-plug versions, which allow testing across the backplane or full interconnect path. The metal shroud can be used in deployable systems to securely hold the cables in place and satisfy MIL-STD-810E and 901D for shock and vibration.