OpenVPX for System Interoperability

Figure 2. A Slot Profile of an OpenVPX (VITA 65 compliant) version of the 6U 5-slot backplane. The profile provides more details on the data signals, utility plane, and more.
If there is any fault with VPX, it was made to be very flexible. This flexibility was beneficial for customized solutions, particularly for how high-speed IO is transported throughout the system. However, it was difficult, if not impossible, to be assured that a board from one vendor would work with one from another vendor, along with a backplane from yet another party. Therefore, the OpenVPX initiative commenced in early 2009 with a goal of providing interoperability definitions for the VPX specification. The initiative was rolled into VITA as the VITA 65 specification, which was approved by ANSI in June 2010.

In short, OpenVPX provides definitions for backplane configurations, which are comprised of slot profiles into which various module profiles can be plugged. The module and slot profiles ensure that a vendor’s VPX boards (modules) have pinouts that are interoperable within the VPX backplane slots. The backplane configuration tells the user which slot profiles are utilized, including information on the data rate, routing topology, and fabric used.

When it comes to backplane functionality, there is very little change. The new standard simply redefined two reserved P0/J0 signals Aux_Clk (+/-) and added one P1/J1 single ended Utility signal of Maskable Reset and redefined the Res_Bus signal to GDiscrete. The Aux_Clk and GDiscrete pins were already bussed anyway, so the change is minimal. Also, the SysCon signal is now configurable.

Let’s take a look at a standard 6U VPX 5-slot Mesh backplane and compare it to an OpenVPX version. Figure 1a shows a 6U 5-slot VPX backplane and 1b shows a sideview of how the J0-J6 connectors are used.

The standard VPX version has pinout charts for P0 and P1 sections with the P2-P6 as “undefined”. Although the P0 and P1 sections have defined pinouts, there are no details in VPX as to the kind of signals such as thin pipes, fat pipes, or ultra thin pipes. Also, the details of the utility plane are not as clear.

In the OpenVPX version of the same backplane, Figure 2 shows the payload slot profile. It provides more information for the data plane section (in yellow), which in this case defines 4 fat pipe lanes. Also, the utility plane sections are clearer. Although this backplane does not have a control plane, if it had one we’d also see this in the payload slot profile, along with the type of signal (thin pipes are commonly used for the control plane).