The purpose of this project was to develop a transfer printing process for the massively parallel integration of III-V lasers on silicon photonic integrated circuits. Silicon has long offered promise as the ultimate platform for realizing compact photonic integrated circuits (PICs). That promise stems in part from the material's properties: the high refractive-index contrast of silicon allows strong confinement of the optical field, increasing light-matter interaction in a compact space—a particularly important attribute for realizing efficient modulators and high-speed detectors.
To date, silicon-photonics applications have had to rely on external laser sources that feed the optical chip through optical fiber, or on flip-chip integration of separately fabricated laser diodes. Neither of those approaches is scalable to very large wafer volumes or to more complex laser designs. Over the last few years, however, the research community has made tremendous strides toward realizing fully integrated laser diodes on silicon, both through wafer-bonding techniques that integrate direct-bandgap III-V epitaxial materials into prefabricated silicon circuits, and through direct epitaxy of III-V semiconductors on silicon.
The goal of this project was to develop a new approach: the integration of high quality III-V epitaxial material (an attribute of wafer bonding) and the possibility to only very locally deposit III-V material on a photonic integrated circuit (an attribute of direct epitaxy). This approach is coined transfer printing.
Wafer bonding, while an established integration method, can lead to inefficient use of the III-V material, and can make co-integration of different III-V semiconductor layer stacks difficult. The transfer printing process tackles these issues. The process rests on transfer printing of micrometer-size semiconductor chips, or coupons, from a III-V source wafer to a silicon photonic target wafer using an automated tool. The method is illustrated in Figure 1.
The process starts with a III-V source wafer that carries a sacrificial layer (In-GaAs) and a III-V device layer. The III-V wafer is patterned into a dense array of coupons as shown in Fig. 1(b) after which the coupons are covered with a polymer tether structure. This structure has openings to selectively etch away the sacrificial layer, such that the III-V device layer is released from the growth substrate. Using a patterned PDMS stamp such coupons can then be picked up (Fig. 1e) and printed (Fig. 1f) to a silicon photonic target wafer. While this process can be done one coupon at a time, the true value of the transfer printing approach is that it allows the massively parallel transfer of III-V coupons to a silicon photonic target wafer. Using multiple and different source wafers, different III-V epitaxial layer structures can be intimately integrated.
A critical step in the transfer printing process is the release of the sacrificial layer InGaAs layer with good selectivity with respect to the InP cladding layers. Table 1 shows the solutions that were evaluated.
The first three options failed to undercut the complete structure of 40μm wide. This is because of anisotropic etching, where a slow etching crystal plane is being exposed when the coupons are aligned along the crystal axes. The HF-based and citric-acid-based etch mixtures rendered a full undercut, but attacked the photoresist based anchors and encapsulation layer. While this could be resolved by using other encapsulation layers, because of the poor selectivity and slow etching speed respectively, these etching solutions were discarded as well. Excellent results were obtained with the FeCl 3:H2O solution at 5°C. Using this etchant, it takes 2 hours to undercut the 40μm wide coupons, with only an InP thickness variation of 20 nm.
After developing the III-V transfer printing process, Si photonic integrated circuits comprising silicon gratings and spot-size converters were designed and fabricated to realize a III-V-on-silicon distributed feedback laser that is coupled to the silicon waveguide layer. A schematic view of such a device is shown in Figure 2. In this case the III-V material is transfer printed onto the planarized silicon waveguide circuit after which the III-V coupon is processed, lithographically aligned to the underlying SOI waveguide circuit. A 50nm DVS-BCB layer is used as an adhesive bonding layer.
This work was done by Gunther Roelkens of Universiteit Gent VZW for the Air Force Research Laboratory. AFRL-0252
This Brief includes a Technical Support Package (TSP).
Laser integration on silicon photonic circuits through transfer printing
(reference AFRL-0252) is currently available for download from the TSP library.
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