Dielectric thin films play a very important role in the development of microelectromechanical systems (MEMS). These dielectric materials often are used as insulating layers in devices, major components in MEMS structures, or even as materials strictly used for fabrication processes in a clean-room environment. In these applications, heat is often a crucial factor. Whether it be heat transfer through a device to stimulate operation, a device being exposed to certain temperatures during fabrication, or any other manner of heat transfer, these thermal processes are critical to device operation in MEMS. As such, thermal properties of these thin film dielectrics, especially thermal conductivity, are very important parameters to insure proper device operation.
Silicon dioxide and photoresist are two dielectrics that are commonly used in MEMS processes and in a cleanroom environment. SiO2 is often used as an insulating layer between a silicon substrate and device stacks on top of the substrate, as well as between conducting layers within the actual device. Photoresist is used in the photolithography process to pattern device layers. It can also be cured using heat and ultraviolet light to be incorporated permanently in devices as an insulator.
At present, thermal conductivity data of silicon dioxide and photoresist at the scale to be studied is very limited. The majority of known values for these materials are for bulk thicknesses.
In comparing known bulk values to those of thinner films, it has been found that a decrease in thermal conductivity results when the size of the test specimen goes from bulk to these thinner films. Also, process conditions between fabrication environments can vary greatly. For example, PECVD SiO2 may be slightly silicon-rich or –poor, depending on the recipe. An increase in silicon content would result in an increase in the thermal conductivity of the dielectric layer. Thus, data from a silicon-rich PECVD would differ from that of a stochiometric PECVD.
The method upon which
this work is based involves a micromesa test structure, seen in Figure 1. The geometry that these mesa structures employ limits the heat path to conduction perpendicular to the surface of the substrate with very little excess heat lost from the sides or top of the structures. This form of testing and measurement constitutes a “direct” measurement of thermal conductivity as DC values are collected from the devices themselves. In this approach, data is collected at “steady state,” which is more representative of the application environment for these materials. Thus, the testing conducted on these structures results in data that relies solely on this vertical conductivity, which is ideal for the purposes of this experiment.
After temperature calibration is complete, a 4-point probe testing method is used by first feeding a small fixed current through the bottom RTD. Concurrently, a larger heating current is forced through the top RTD to provide a heat flux through the dielectric layer. Although some heat is generated in driving current through the bottom RTD, it is minimal in comparison to that of the top.
The test devices were fabricated within a cleanroom environment. A thin, 0.5-μm silicon dioxide layer was first deposited using plasma-enhanced chemical vapor deposition (PECVD) onto a polished silicon substrate. This SiO2 layer is used as an electric insulator between the silicon substrate and the bottom RTD. On top of this layer, a metal RTD layer was patterned using photolithography. A 100 Å titanium adhesion layer was sputtered onto the oxide, followed by an 850 Å platinum layer to act as the RTD. The excess metal was then removed through the use of acetone during the liftoff process. The silicon dioxide layer of interest was then deposited on top of this RTD through the use of PECVD. Three different oxide thicknesses were patterned: 1.18 μm, 1.67 μm, and 2.24 μm.
On top of this SiO2 layer, the top metal heater was patterned through the use of photolithography in the same manner as the bottom RTD. A 100 Å titanium adhesion layer and a 1700 Å platinum layer were then sputtered on, before the excess metal was lifted off through the use of acetone once again. The completed wafers can be seen in Figure 2. These wafers contain 6 die with 9 devices per die for each silicon dioxide thickness. On each die, the device lengths are 1 mm, 2 mm, or 4 mm, while the device widths are 50 μm, 100 μm, or 200 μm. This is to ensure as much variation in testing results as possible to elucidate geometrical and/or edge effects.
This work was done by David J. Howe and Brian Morgan of the Army Research Laboratory.