There are existing wideband communications systems that were built using field-programmable gate array (FPGA)-based software-defined radio (SDR) designs. Despite the inherent advantages of these systems, some are functionally restricted by limited output bandwidth. An FPGA-based SDR was designed that can compress sampled intermediate-frequency (IF) signals. The compression scheme used in the final design is based on flexible operator-defined, time-frequency bins and independent energy thresholds for each bin.

The FPGA-based SDR can compress sampled wideband IF signals based on reprogrammable parameters. The design was developed around the concept of independent, operator-defined time-frequency bins and evaluation of the energy in each bin. Although the design concept incorporated bins with varying time-window periods, the final design was simplified so that each bin used the same period.

Xilinx’s System Generator software was utilized to develop and test the behavioral definition of the design. The tool was also used to synthesize the design, perform the place-and-route functions, and generate the .bin file that provides the FPGA’s configuration information. The development tool provided a layer of abstraction that reduced the requirement for in-depth knowledge with respect to HDL coding. If the design required management of internal hardware clocks, then the ability to code in an HDL would have been more critical.

The SDR was developed for a Virtex-4 FPGA architecture. While this can potentially affect its portability, the SysGen FFT v4.1 module was the only component used that is not backward-compatible to the Virtex-1.

Two versions of the algorithm were built and tested. The first utilized an 8-point FFT, which simplified analysis efforts. The second version utilized a 1024-point FFT and helped verify the requirements for scaling the design. Both versions were tested using single- and multi-frequency input signals, without restrictions on the output memory. This ensured the basic compression scheme operated properly. Then, the 1,024-point algorithm was used to verify the design and automatically adjust its operations based on the available storage capacity. Testing provided insights regarding the effects and workarounds for machine epsilon. It also verified the design’s desired functional operations.

Although the final design operated as expected, it has performance limitations that should be recognized and considered. All of the development tests were conducted such that the digital input frequencies and the defined bin frequencies were an exact match. If frequencies that did not match the FFT window, i.e., frequencies that did not have an integer number of cycles per FFT window, were used, there would be a slight smearing effect in the frequency domain. It is assumed that this effect is minor, and would not significantly impact the efficacy of the algorithm. The tests also assumed the input signal and the SDR shared the same sample frequency. If this were not the case, the implementation could correct for this with interpolation or decimation, or similar multi-rate signal processing.

This work was done by Durke A. Wright of the U.S. Navy. For more information, download the Technical Support Package (free white paper) at www.defensetechbriefs.com/tsp under the Electronics/Computers category. NRL-0039


This Brief includes a Technical Support Package (TSP).
Field-Programmable Gate Array-Based Software-Defined Radio

(reference NRL-0039) is currently available for download from the TSP library.

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This article first appeared in the April, 2010 issue of Defense Tech Briefs Magazine.

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