For air, space, and ground-based systems, there is a clear need for high-performance, lightweight, low-power, highly reliable computing on data-intensive applications. A data-intensive application is one in which there is a very large volume of data, which is often accessed in irregular patterns. Yet, despite the fact that application-specific integrated circuits (ASICs) are becoming more memory-intensive, commodity memory and ASIC design and manufacturing technologies are still on divergent paths.
This work explored the use of regular fabrics for lowering the barrier to using commodity memory technology for memory-intensive ASICs. A regular fabric is a system of circuits and design methodologies that best utilizes the simple, regular patterns that can be reliably printed for logic, memory, and analog circuits with a single, compatible, subwavelength lithography setup. In particular, results show that laying out logic circuitry on regular grids that are based on memory array spacing can substantially improve the manufacturability of memory-intensive ASIC designs. Regular fabrics are especially conducive to ebeam lithography, where electron beams transcribe patterns directly to the silicon wafer, without the use of photolithographic masks. Because of this, regular fabrics provide a path for cost-effective, low-volume production by reducing mask cost.
Given the base technology for implementing memory-intensive ASICs that regular fabric provides, a further challenge is giving architects the tools to evaluate tradeoffs and explore the range of possible designs for complex, heterogeneous ASIC designs. Such designs may include many processor cores, interconnection networks, I/O components, and multiple varieties of memory, including 3D stacks or quilts. To address this challenge, both midrange and high-level tools were developed for modeling power, area, and timing in multi- and many-core systems.
High-level analysis tools can reduce design cycle time, cost, and risk by enabling design space exploration for area, speed, and power for multicore, memory-intensive systems. System-level tools that use simple heuristic and analytic models, as well as “midrange” tools that run in conjunction with a standard architectural simulator, are both necessary. The midrange tool, named McPAT (Multi-core Power, Area and Timing), uses circuit-level models coupled with statistics from an architectural simulation to obtain fairly accurate predictions. The high-level tools use simpler models, but permit rapid exploration and characterization of a broad design space.
Unlike prior tools, which were tightly integrated with specific performance simulators, McPAT uses an XML interface to decouple the architectural simulator from the power, area, and timing analysis, so that it can be readily used with a variety of simulators. McPAT’s power models account for dynamic power, subthreshold leakage, and gate leakage, as well as short-circuit power, using calculated timing information to determine the interval when both the pull-up and pull-down devices are conducting. It is also the first processor power modeling environment to include both power gating and clock gating, as well as support for P-state and C-state power management schemes. In providing these capabilities, McPAT supports architects in exploring a broad design space for future multicore and many-core systems.
This work was done by Jay Brockman, Peter Kogge, and Michael Niemier of the University of Notre Dame; and Larry Pileggi of Carnegie Mellon University for the Air Force Research Laboratory. For more information, download the Technical Support Package (free white paper) at www.defensetechbriefs.com/tsp under the Electronics/Computers category. AFRL-0140
This Brief includes a Technical Support Package (TSP).
Memory-Based, Structured, Application-Specific Integrated Circuit (ASIC)
(reference AFRL-0140) is currently available for download from the TSP library.
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