A project called “System on a Chip Real-Time Emulation” (SOCRE) was undertaken to develop and demonstrate a methodology of simulation of operation and semiautomated design of complex mixed-signal (analog/digital) integrated circuits (ICs). The methodology includes the use of a simulation engine (consisting of computer hardware and software) for real-time emulation of a designed IC, in conjunction with an automated design flow that enables automated or semiautomated synthesis of a final design and automated or semiautomated fabrication of the ICs of the designed IC without need for manual reentry of a description of the design.

The Initial Layout of a 256-Antenna Correlator IC (shown here with a portion of memory and logic circuitry at greater magnification) was generated automatically in a demonstration of the methodology described in the text.

The methodology was built on a foundation consisting of the Berkeley Emulation Engine 2 (BEE2), which is a scalable, reconfigurable computing module that includes field-programmable gate array (FPGA) processing submodules and high-speed memory submodules connected via high-speed serial and parallel links, and is equipped with software that provides an environment for developing and debugging the software that would be executed in the IC being designed. The BEE2 enables real-time evaluation of architectures and algorithms, as well as real-time verification of performance before the designed IC is built. The combination of the BEE2 and automated design flow provides a rapid-prototyping capability that facilitates and accelerates the process of designing and building an IC. A given hardware design and software implementing complex algorithms to be executed in the hardware can be automatically synthesized and tested in real hardware and/or in a BEE simulation that is of such high quality that it can be regarded as equivalent to testing in real hardware.

The methodology was demonstrated by applying it in the design of two ICs: One was an IC implementation of a cross-bar-based multiple-antenna correlator, which is a high-performance, analog- signal-input/digital-signal-processing subsystem typically used in processing signals received by multiple radio-astronomy antennas (see figure). The other was an IC implementation of a real-time image-processing subsystem that accepts video input, detects edges in the video image, and generates an edge image that can be displayed alone or superimposed on the original video image. In these applications, it was demonstrated that a single design description can be mapped automatically, both to such FPGA targets such as the BEE2 emulation platform and to system-on-a-chip design software libraries (which can include intellectual property optimized for implementation in foundries), with little or no redesign effort. The ability to retarget a design to foundry-optimized intellectual property makes it possible for designed ICs to be more area-, speed-, and/or power-efficient than they would be otherwise.

This work was done by John Wawrzynek, Robert Brodersen, and Brian Richards of the University of California for the Air Force Research Laboratory. AFRL-0021


This Brief includes a Technical Support Package (TSP).
Real-Time Simulation and Semiautomated Design of Complex ICs

(reference AFRL-0021) is currently available for download from the TSP library.

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This article first appeared in the April, 2007 issue of Defense Tech Briefs Magazine.

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