A mixed-signal receiver on a chip (RoC) now undergoing development is intended to be a prototype of the front ends of lightweight, compact, low-power, relatively inexpensive heterodyne radio receivers for future phased array radar systems. [As used here, "mixed-signal" refers to a design for utilization of both analog and digital signals, and "front end" signifies the portion of a heterodyne receiver that processes the raw radio-frequency (RF) input to produce an output at an intermediate frequency (IF) that is the difference between the RF and the frequency of a local oscillator (LO).] The RoC will include two integrated circuits, denoted IC1 and IC2 respectively, that comprise integrated chipsets designed and fabricated on the basis of the International Business Machines 7HP generation of SiGe bipolar complementary oxide/semiconductor (BiCMOS) technology.

The Front-End Mixed-Signal Receiver on a Chip as envisioned would include IC1 and IC2 and some other components, all packaged in a multichip module.

Each of IC1 and IC2 was packaged in a multichip module (MCM) by use of a flipchip fabrication process. In the envisioned fully developed version, both IC1 and IC2 would be packaged in the MCM along with other components (see figure). In the fully developed version, the output of IC1 would be a first-IF signal that would be fed as the RF input to IC2, which would put out a signal at a second IF.

IC1 is designed to convert from a single- ended RF input in the X band (between 8 and 12 GHz) to a single ended first-IF output in the S band (2 to 4 GHz). Components in IC1 include an X-Band low-noise amplifier, a high-pass filter, a lead-lag splitter (essentially, a single- input, dual-output phase shifter/balun unit), a balanced amplifier, a double-balanced diode mixer, a band-pass filter, and a buffer amplifier. In a test, the packaged IC1 exhibited a gain between 22 and 23 dB gain across a first-IF range from 3.7 to 4.3 GHz.

IC2 is designed to convert from the single-ended first IF to a differential output signal at the second IF, which is in the L band (1 to 2 GHz). Components in IC2 include two lead-lag splitters; a first balanced amplifier; a double-balanced diode mixer; a non-reflective band-pass filter; a buffer amplifier; a high-pass filter; a second, ultra-linear balanced amplifier; and low-pass filters. In a test, the packaged IC2 exhibited a gain of 28.63 dB gain when operating at an RF of 4 GHz and an LO frequency of 3 GHz to produce a second IF at 1 GHz.

This work was done by Gregory Creech, Tony Quach, Pompei Orlando, Vipul Patel, Aji Mattamana, and Scott Axtell of the Air Force Research Laboratory. For further information, download the free white paper at www.defensetechbriefs.com under the Electronics/Computers category. AFRL-0019

This Brief includes a Technical Support Package (TSP).
Front-End Mixed-Signal Receiver on a Chip

(reference AFRL-0019) is currently available for download from the TSP library.

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This article first appeared in the February, 2007 issue of Defense Tech Briefs Magazine.

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