By definition, “heterogeneous integration” (HI) refers to the integration of dissimilar components on a common platform. The term is extensively used in very diverse applications to encompass efforts to make previously separate functions operate together by an intimate fusion of components. It can mean a seamless integration of previously incompatible software, database, drugs or machine parts. The particular definition that applies here is the integration of dissimilar sensor components onto a common substrate to make new compact components that provide enhanced characteristics.
IEEE defines Heterogeneous Integration to be “the integration of separately manufactured components into a higher-level assembly that, in the aggregate, provides enhanced functionality and improved operating characteristics”. In this definition, components should be taken to mean any unit whether individual die, micro-electromechanical systems (MEMS) device, passive component and assembled package or sub-system that are integrated into a single package. The operating characteristics should also be taken in its broadest meaning including characteristics such as system level performance and cost of ownership.
Heterogeneous integration includes a variety of technology components ranging from transistors and their fabrication methods to testing and packaging. In thinking about the evolution of electronic systems, opinions are often formed by relying solely on the progress of “digital technologies” whose evolution is often governed by “Moore’s Law”. This empirical rule predicts that the number of transistors of an (digital) electronic system will double every two years. The transistor geometries are expected to continue shrinking to accommodate ever higher density circuits following the well-known technology roadmaps such as the ITRS. These roadmaps help synchronize technology development efforts by providing guidance to research communities and funding agencies. So far, the use of such roadmaps has been very successful in improving resource efficiencies and providing predictions in the capabilities of future systems.
Until recently, compliance with Moore’s Law used to require simple geometrical shrinkage (geometric scaling) of transistor feature sizes so that more transistors can be accommodated on a given chip size. Smaller transistor gate lengths also improved the device performance by reducing the transit time for electrons between electrodes. This trend continued unbroken until about 2004, when it became apparent that simply cramming more transistors into an area is not the best way to improve (digital) system performance. Delays due to metal interconnects and the formation of thermal hot spots severely limited the performance gains obtained by density improvements. Currently, the circuit density is still increasing but the operation frequency is saturating, as shown in Figure 1.
Other scaling approaches are being investigated to increase chip performance without necessarily reducing transistor size, in which case the circuit density increase will saturate. This new reality can be seen by comparing the device feature size reduction expectations of the 2013 ITRS roadmap with the more recent 2015 ITRS roadmap expectations as shown in Figure 2. While previously it was expected that the physical gate length shrinkage would continue until at least 2028, now it is believed that it will saturate in 2021 when the 9nm node is reached. Any further increase in circuit density will now come from 3D architectures. The circuit density improvements by 3D stacking of similar circuits (functions) is “homogeneous integration”.
The same approach can be applied to the integration of digital circuits with other types of circuits. These circuits may include functions that can be best implemented by a different technology node. They may include functions that are implemented in technologies that do not follow Moore’s Law (such as analog/radio frequency (RF) circuits). They may indeed include functions that are not even electronic (such as optical, mechanical or acoustic). The integration of these diverse function circuits is “heterogeneous integration”.
This work was done by Dr. Burhan Bayraktaroglu for the Air Force Research Laboratory. AFRL-0283
This Brief includes a Technical Support Package (TSP).
Heterogeneous Integration Technology
(reference AFRL-0283) is currently available for download from the TSP library.
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