Historically, the military has used special- purpose Global Positioning System (GPS) radios for radio navigation. This has the disadvantage of locking users into fixed technology solutions designed to meet a fixed set of requirements. Software Defined Radios (SDR) have the advantage of being able to easily adapt to provide new capabilities using current-generation technology. Continued improvements in SDR technology are enabling their use for Global Navigation Satellite System (GNSS) applications that require small-form-factor, low-power designs. This has the added benefit of allowing the signal processing algorithms for future GPS signals to be included in the GNSS SDR design without changing or modifying the hardware of the GPS receiver.
A GNSS SDR reconfigurable architecture was developed that leverages the flexibility of a SDR to re-use resources for processing the different GPS signals. Recent advances in the GPS constellation have resulted in additional signals being made available for both military and civil applications. The modernized GPS signal structure includes signals broadcast on three frequencies (L1, L2, and L5) and including both the legacy GPS modulation codes (C/A and P(Y)) and also additional civilian codes on L2 and L5 (the L2c and I5/Q5 codes); and also additional military codes on L1 and L2 (M-code).
In order to obtain a good navigation solution, it is only necessary to operate enough tracking channels in a GNSS receiver to obtain sufficient satellites in view to achieve good geometric dilution of precision. That generally only requires between 4-6 satellite signals. The GNSS SDR architecture described here allows for dynamic reconfiguration of the SDR channel resources to track different GNSS satellite codes and frequencies. With this approach, the flexibility of the SDR can be leveraged to implement a full-function GNSS receiver capable of leveraging any of the GNSS signals without requiring massive numbers of parallel channels to operate.
NAVSYS leveraged GPS SDR development efforts to design a miniaturized SDR architecture with low-power design features and dynamic reconfiguration of the receiver channels to allow different GNSS frequency bands and signal codes to be processed by each channel. The SDR design being developed is flexible enough to cover the GNSS frequency bands for L1 and L2 operation, and the new civil L5 frequencies using either the military or civil codes.
The GNSS SDR uses three RF channels to receive the L1 (1575.42 MHz), L2 (1227.6 MHz), and L5 (1176.45 MHz) signals. The digital outputs from each of these RF channels, termed Digital Antenna Elements (DAEs), are then provided to the SDR baseband processor. If any RF channel is not being used, it will be disabled to save power.
The entire receiver baseband processing is being implemented on a single Xilinx Virtex-6 FPGA (Field-Programmable Gate Array). The FPGA is initially loaded from external flash memory with a base configuration to enable communication to a host input device. The user would then be able to select any combination of GNSS codes to be tracked by the six receiver channels. Utilizing Xilinx dynamic partial reconfiguration, the receiver channels are loaded from external flash memory and configured by the host to acquire and track specific satellite signals.
If the user decides to track different GNSS codes, that change can be made at any time. Once the system receives the command to reconfigure from the host, the FPGA will read the required partial reconfiguration bit files from external flash RAM and use that to configure the selected channel. RF channels and encryption key management modules will be enabled or disabled as needed. Tracking operations of the other five channels will not be affected by the reconfiguration.
Using Xilinx’s dynamic reconfiguration capability, each of the FPGA channels in the GNSS SDR can be dynamically reconfigured to track a different GPS frequency or satellite signal. The common base configuration is programmed into the FPGA when it first boots from the flash memory. The GNSS SDR user can then decide what processing will be required in each of the six reconfigurable channels. The appropriate FPGA bitstream is then loaded into each of the dynamically reconfigurable areas from the flash memory. The size of each of the reconfigurable regions is fixed and determined by the complexity of the largest processing algorithm estimates of the required FPGA resources for each of the supported GPS signal types. The partial bitstream loading is done through the Xilinx Internal Configuration Access Port (ICAP). This internal port allows for the reconfiguration image to be decrypted and verified before being applied without ever leaving the FPGA where it could be tampered with.
This work was done by Alison K. Brown and Nigel Thompson of NAVSYS Corp. NAVSYS-0003
This Brief includes a Technical Support Package (TSP).
Dynamically Reconfigurable Software-Defined Radio for GNSS Applications
(reference NAVSYS-0003) is currently available for download from the TSP library.
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