Tech Briefs

These hybrid circuits are suitable for memory, FPGA, DSP, and analog applications.

The memristor is the fourth fundamental passive electronic device in addition to the resistor, capacitor, and inductor. By integrating with complementary metal oxide semiconductor (CMOS) devices, memristors show promise for development of revolutionary new nanoelectronic computing architectures with significantly reduced size and extremely low consumed power. The proposed effort explores a novel, high-payoff nanotechnology area that exploits crossbar nanoelectronic logic elements as well as the recently demonstrated phenomena of memristance. Specifically, the goal of this project was to explore CMOS-memristor hybrid nanoelectronic circuits for memory, FPGA, DSP, analog, and neuromorphic applications.

Crossbar computer logic architectures are complex matrices of interconnected nodes that show great promise for scalability, size, weight, and power issues. In their simplest form, crossbar junctions consist of two nanowires (less than 100-nm wide) that physically “cross” each other. The junction between these nanowires is composed of a junction material with tailored transport properties. Crossbar logic elements enable massively parallel computations with the potential for a reduction in power consumption and size by up to 2-3 orders of magnitude. Crossbar computing is also tolerant to hardware defects due to its intrinsic, network-onchip flexibility to re-route around defects.

In order to take advantage of these new memristive properties, it is necessary that memristive nanoelectronics be successfully integrated with current CMOS process technology. The electronic transport properties of memristive nanoelectronics driven by CMOS circuits will provide critical insights into subcircuit designs and subsequent advanced architectures.

The specific tasks of the project included: material selection, integration flow development, circuit design and simulation, and demonstration vehicle fabrication/testing. Materials selection and integration flow development was performed in conjunction with the CNSE Center for Semiconductor Research. Fabrication engineers were consulted for compatible back end of the line (BEOL) materials with memristive properties and vertical integration design built off of previous work at CNSE for CMOS transistor fabrication.

Modeling and simulation were performed using commercially available software including Verilog-A and SPICE. Novel code was written to simulate one transistor/one memristor (1T1R) devices, as well as an FPGA routing circuit utilizing memristive elements. Memristor electrical behavior was modeled as bipolar switching, based on measurements of individual memristive devices. All other device characteristics were taken from standard CMOS devices using a standard 65-nm device platform. FPGA/memristor demonstration devices were fabricated by manually connecting individual memristors with transistors using wire bonding to achieve an FPGA routing switch that could potentially replace an SRAM-based routing switch. This breadboard device was then tested in an Agilent 1500 probe station with associated analysis hardware/ software.

In this project, the design and simulation of 1T1R structures was completed. The Verilog A model was developed for memristor for SPICE simulation. Therefore, the SPICE-Verilog A simulator can be used to analyze the performance of CMOS-memristor 1T1R cells for memory applications.

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