Analyzing microelectromechanical system (MEMS) switch behavior is a new field of study that guides the production of MEMS switches. One issue of primary importance is the degradation of contact resistance over the lifetime of the device, and whether small variations in the resistance initially can be prognostically used to predict future performance. Unfortunately, commercially available equipment is limited by its data collection rate, and is not a realistic option to examine every cycle of a switch expected to potentially survive for several trillion cycles. In addition, these tests must be performed on tens to hundreds of switches, necessitating the need for a parallel measurement solution.
To overcome these challenges, a field-programmable gate array (FPGA)-based solution is being developed. The FPGA chip, coupled with a 16-bit dual-channel AD/DA converter, will serve as the input source to each switch and the measurement system, diagnosing contact performance every cycle. Although customizable to any switch configuration, the purpose of this project was to determine the feasibility of testing single-pole-single-throw (SPST) RF-MEMS switches, which contain four terminals: bias/actuation, RF-input, RF-output, and ground.
The project was broken down into three phases. First, the algorithms necessary for the system to function, both in terms of testing and meaningful data display, were developed. Next, based on those algorithms, the FPGA implementation options, direct HDL programming, and software-defined microcontroller usage were analyzed to determine the appropriate system to reduce implementation complexity while maximizing scalability. Finally, the initial circuit code was created to demonstrate a proof-of-concept system functioning on a single switch.
Switch behavior was analyzed using a digital circuit synthesized on an FPGA chip. The chip has two outputs: the first output biases the MEMs switch; the second output feeds a digital-to-analog (DAC) converter that provides the drive signal for testing the switch. It opens and closes the switch repeatedly at approximately 20 KHz. An external resistor of 10 kΩ is connected in series with the switch. The analog output voltage across that resistor is measured (in both open and closed states) and fed into an analog-to-digital converter (ADC). This bit stream is then fed into the FPGA, which will calculate the switch resistance based upon the voltage drop across the external resistor, the voltage drop across the series connection of the external resistor and the switch, and the resistance of the external resistor.
All parameters, such as the bias voltage, are entered into the chip using a software application on a computer. This FPGA-based instrumentation presents a higher-frequency measurement capability for MEMs switches than is currently available commercially. By using low-cost FPGAs, this setup can easily be scaled up into as many as 100 parallel tests that will enable reliability studies that require hundreds of millions of switch cycles.
The apparatus looks for two types of general failures: temporary and permanent. Both types of failures have two possible modes: stuck open and stuck closed. Once a temporary failure is detected, the switch resistance and num- ber of cycles are sampled. After crossing a set limit of consecutive temporary failures, the switch is considered as having permanently failed.
A software-based application was used to prototype the primary VHDL module. The VHDL module was responsible for producing each output voltage and measuring the response of the switch. In the final module, each input voltage is converted to a 16-bit array, which will be sent to the storage memory via Ethernet.
This work was done by Stanley Karter and Tony Ivanov of the Army Research Laboratory. ARL-0131
This Brief includes a Technical Support Package (TSP).
Microelectromechanical System (MEMS) Switch Test
(reference ARL-0131) is currently available for download from the TSP library.
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