Content addressable memory (CAM) is one of the most promising hardware solutions for high-speed data searching and has many practical applications such as anti-virus scanners, internet protocol (IP) filters, and network switches. Since CAM stores the data in its internal memory elements and compares them with the search data in parallel, it can achieve much faster speed compared to the software lookup.
There are two types of CAM: binary CAM and ternary CAM (TCAM). Especially, TCAM has not only two binary states (‘0’ and ‘1’) but also an additional “don’t care” state in which it performs the wild match. The most important qualification for a TCAM cell is fast operation speed for data searching. Due to this reason, static random access memory (SRAM) has been widely used in memory elements of the conventional TCAM cell, even though it has high bitcell cost, typically requiring 12-16 transistors per cell as shown in Figure 1.
However, recent trends in electronic applications, such as internet of things, big data, wireless sensors, and mobile devices, have begun to focus on the importance of energy consumption. The SL (S) large SRAM-based TCAM cell inevitably increases capacitive loading of match lines (MLs) and search lines (SLs), which in turn raises dynamic power of search operation. Also, as complementary metal-oxide-semiconductor (CMOS) shrinks to nanometer-scale, the other major issue has emerged: a high standby power due to leakage current. A scaled-down channel length increases the leakage current, and hence the use of SRAM in TCAM applications is not a sustainable pathway.
The first approach to achieve a low-power and high-density TCAM with a comparable searching speed is utilizing emerging memory technologies. Although emerging nonvolatile memories, such as resistive RAM (ReRAM), phase-change RAM (PCRAM), and spintransfer RAM (STT-RAM) have been proposed for TCAM applications, using MeRAM as a memory element of TCAM is being proposed because MeRAM out-performs other memory technologies in terms of speed, energy, and density. Typically, a MeRAM cell consists of one transistor and one voltage-controlled magnetic tunnel junction (1T-1MTJ) as shown in Figure 2 where the bottom layer of the voltage-controlled magnetic tunnel junction (VC-MTJ) is connected to the drain of the access transistor, and the top layer is connected to the bit line (BL). The size of the access transistor in MeRAM can be reduced further in that the voltage-driven switching ideally does not require the flow of current. Thus the bit cell array of MeRAM can achieve higher density compared to other families of magneto-resistive RAM (MRAM). Also, the thickness of the tunnel barrier is relatively thick, practically reducing ohmic dissipation during the write operation.
This work was done by Kang L. Wang, University of California, Los Angeles, for the Air Force Research Laboratory. AFRL-0257
This Brief includes a Technical Support Package (TSP).
Content Addressable Memory (CAM) Technologies for Big Data and Intelligent Electronics Enabled By Magneto-Electric Ternary CAM
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