Radar receiver design is seeing an increase in the number of digital tuning and digital signal processing (DSP) functions moved from back-end single-board computers into fixed front-end hardware logic. The front-end receivers have become much more complex and difficult to design. This results in two rising challenges for digital design engineers: prototyping and testing highly sophisticated receivers, and designing with limited budgets for both power and heat dissipation.

Structured ASICs are made up of custom top layers and standard base layers.

An efficient "one stop" FPGA-to-ASIC design flow transition provides lifecycle solutions for both of these problems. The flexibility and prototyping advantages of FPGAs (field-programmable gate arrays) allow all of the advantages of embedded systems programmability, while the transference of FPGA design to a structured ASIC (application-specific integrated circuit) allows for increased performance and reduced power and size footprint. This maximizes transmitter/receiver performance, while minimizing power and heat.

FPGA-to-ASIC transitions have been exercised for the past two decades by many digital logic designers based on changes in market requirements, or when systems transition from prototype to fixed configuration, full production. The cost and schedule successes of these transitions depend on complexity, tolerances, and the working relationship between FPGA designers and ASIC designers.

Where the advantages of making this transition from FPGA to structured ASIC in a system are usually evident, the cost and risk of making this transition are the deciding factors for engineering managers. Once these costs are both predictable and low, sensor board designers can confidently make FPGA-versus-ASIC decisions as part of their standard design flow.

Prototyping Radar Systems

The National Missile Defense Ground Based Radar Prototype (NMD-GBR-P) is an example of a long-lead radar prototype program. The NMD-GBR-P was designed to prove out active and passive array technology for missile defense. This program also sought to test and develop the intricate integrated activities of tracking, C4I, and battle damage assessment of a missile defense system, as well as reduce system risk. From FY 1996 to 2004, over $200 million was spent on the radar prototype alone.

Distributed sensor systems and radar data fusion are other areas where prototyping and iterative design changes are essential. These applications are driving more sophisticated modeling systems, and are well-suited to FPGA and "blue board" prototypes. These early prototypes also help software developers innovate with better algorithms and software tactics for best-fit detection and tracking, such as Space-Time Adaptive Processing (STAP). As an additional benefit, prototypes allow designers to innovate architectural improvements to increase the maintainability of the system for increased design life.

FPGA-to-ASIC Die Change

Early prototyping and technology assessment is no longer the domain of just large systems developers. Even small radar and sensor systems are composed of multiple radiating elements and often complex Fast Fourier Transforms (FFTs) for beam forming. Language-based modeling systems are likewise becoming more sophisticated, but are sometimes limited in modeling algorithmic efficiency and speed. After the significant cost and effort in proving out a system through modeling and prototyping, faster paths from prototype to production are needed.

Large-scale multi-use radars, such as the Multifunction Phase Array Radar (MPAR) concept, will certainly require a large degree of multi-mission prototyping. Such a radar system, if implemented across several national radar missions, will also benefit from enough receiver card volume to see per-unit cost advantages from structured ASIC design approaches.

The roles of the researchers and laboratories have become prominent in radar systems development, as they have a greater set of responsibilities in helping to make systems sustainable, testable, and fieldable. Architecting a solid FPGA-to-ASIC system design transition is one way to contribute.

What is a Structured ASIC?

A structured ASIC has application-specific upper layers, often designed based on an FPGA netlist. A structured ASIC is intended to fill the needs of programs that require price and performance points between FPGAs and standard-cell ASICs or ASSPs (application specific standard products). FPGA vendor Altera Corp. offers services to transition a customer's FPGA design into a HardCopy structured ASIC. The process of transitioning an FPGA design to a structured ASIC involves an extensive library of HCell macros. Each of these have been pre-characterized and pre-verified. These map logic from the FPGA adaptive logic modules (ALMs) into ASIC gates, using only the logic specified in the FPGA design. This is done without modifying the FPGA design or netlist in any way; the FPGA routing information is preserved in the design.

The structured ASIC approach has several advantages over the traditional standard-cell ASIC transition that has been conducted in the past for military sensor systems. The primary advantage is having a single vendor offering technical assistance in FPGA design, as well as transitioning to a structured ASIC. Second is the guarantee of both package and pin compatibility between FPGA and ASIC. Power estimates can be performed on FPGA and structured ASIC using the same power estimation tool. Finally, the most important reason to consider the structured ASIC design path is about risk management. A standard cell ASIC is an engineering effort with high hardware expenditures in the case of errors in chip layout, while the risks of error in transferring an FPGA netlist to the structured ASIC netlist are virtually non-existent.

Transition from FPGA to ASIC

Functional Comparison of Standard Cell ASIC vs. Structured ASIC

Traditionally, the design trade-off in an engineering design between FPGAs and ASICs has been made on the basis of cost, development time, and risk. Designing hard chips is time-consuming, expensive, and errors often lead to expensive remanufacturing. Only 39% of ASIC designs are bug-free at first silicon. FPGAs reduce this design risk, though that comes with larger device size, less power efficiency, and lower speed performance.

Miniaturization and cooling challenges are making size and power into critical design parameters. Therefore, a cost-versus-benefit trade of migrating a prototype design from FPGA-to-ASIC should be made when moving from prototype to manufacturing and deployment.

It is important to note that the decision to pursue the receiver electronics design in an FPGA flow does not require any initial design constraints for the FPGA designer. The decision to transfer to a structured ASIC design can be made well into pre-production, after all prototyping, proof-of-concept, and algorithmic testing is performed using the FPGA design and test bench.

The advantages of this transition from FPGA-to-ASIC allow system design to become more compact, as the FPGA footprint and cooling requirements are reduced. However, the transition does not require a receiver board re-spin, as the structured ASIC can be designed as a pin-for-pin replacement for the FPGA in the same package.

Additional advantages of an ASIC implementation in advanced sensor systems include immunity to single event upsets (SEUs) and improved Mil-Temp performance. ASIC implementations sometimes require additional compliance with International Trade in Arms Regulations (ITAR).

Silicon Re-spins in ASIC Design (Source: Collett International Research)

The design transfer from FPGA-to-ASIC demonstrates significant advantages in design flow over developing a new integrated circuit. The same code synthesis can be used for both the FPGA and structured ASIC design. Design tools then allow designers to perform separate physical optimizations for a targeted FPGA and an ASIC die. This results in two different netlists that can be used for either FPGA implementation or ASIC design performed at the structured ASIC design center. A receiver design can progress through several prototype versions within a radar test bed before returning to the synthesis step and pursuing a structured ASIC device.

Due to the complexity of radar systems design, engineers should maintain as much flexibility as possible through system definition and prototyping with respect to digital logic elements. Later, when systems manufacturing and production systems are made, the program manager still has several options to meet changing requirements on cost, power, heat, performance, and form factor. FPGAs offer maximum design flexibility, while the design transition option to structured ASIC increases that flexibility for radar systems designers.

This article was written by J. Ryan Kenny, technical marketing manager in the military and aerospace business unit of Altera Corporation, San Jose, CA. For more information, click here .