The simulation of electromagnetic (EM) and thermal properties of semiconductor and substrate materials has been demonstrated to be particularly helpful in the optimization of the design of Monolithic Micro wave Integrated Circuit (MMIC) power amplifier (PA) modules. Various design challenges, however, have to be dealt with in specific ways, and may require efficient approaches that accommodate reasonable approximations in the development and troubleshooting phases. EM and heat transfer analysis at the semiconductor device structure level allows building accurate models for simulation tools.

Figure 1 (a): Feedback circuitry including NPN transistor-based power detectors, and (b) the RF amplifier circuitsincluding the RF power transistor array (SkyworksSolutions, Inc. GaAs HBT process).

In a time-constrained development environment, or for the training of highly qualified personnel, there is also a need for an approach that allows the designer to start with a simplified but efficient characterization of the EM and heat transfer effects at circuit building blocks level, and with the option of gradually including various structural elements towards a complete physical representation of the system under test.

COMSOL Multiphysics™ software was used in a design example that involved the need for estimating the effects of temperature on on-chip RF power detectors, given the RF power transistor array geometry.

Optimizing the performance matching between on-chip transistor- based RF power detectors may have a big impact on circuit behavior in some MMIC designs. The NPN HBT transistor used in this design typically offers base-to-emitter voltages (VBE) that vary by about -1.2mV/ºC. Therefore, in an envelope comparator circuit using strongly NPN-based nonlinear envelope detectors that deliver a feedback error signal in the order of a few millivolts only, a difference of several degrees between the two detectors may impair the feedback error correction process, even if sophisticated compensation circuit techniques are used.

Power Detectors and RF Transistor Array Design

The first IC, which includes two NPN transistor-based power detectors, is shown in Figure 1(a), together with an enlarged view of the detector area. Note that in this design, a very conservative approach of placing the two detectors as close as possible for matched performances has been used, with the goal of obtaining as symmetrical EM coupling and heat transfer as possible. The second IC, which includes the RF power transistor array, is shown in (b).

In the logical extension of merging the two designs on a single GaAs HBT chip, an optimization of the location of the two detectors needs to be performed. The conservative approach of placing the two detectors as close as possible might not be the best solution, because it requires the routing of the output signal towards the input section, which may affect stability and translate into sacrificing RF performances (this becomes even more severe at millimeter wave frequencies); and signal integrity in the input detector branch and/or in the output detector branch might be degraded (e.g. due to EM coupling from other signal traces on the chip) in trying to constrain the design of the layout in order to meet the requirement of having the two detectors very close to each other.

Therefore, a layout design at circuit blocks level based on EM and thermal transfer analysis should allow a better optimization of the MMIC layout.

Heat Transfer Simulation

Figure 2: COMSOL drawing showing the transistor locationsfor heat transfer simulation.

Heat transfer simulation was conducted for the estimation of temperature variations across the GaAs chip. For the purpose of this simulation, only the RF transistors in the power stage and the two detectors are included, and the hypothetical scenario with no heat sink is considered. The location of the 96 NPN RF transistors (Figure 1b) is shown in the COMSOL-generated drawing of Figure 2.

The locations of the two envelope detectors are also shown in Figure 2, and are representative of the layout solution under evaluation: minimizing the EM coupling between the two detector branches, and preserving signal integrity by placing the input detector close to the PA’s RF input, and the output detector close to the output stage. The RF power transistors have also been grouped into four equal size blocks to accommodate some layout requirements.

Figure 3 shows a heat transfer simulation using COMSOL, in the case where the output RF transistor array is constantly dissipating a total power of 1 Watt, equally shared among the 96 transistors. Assuming a power efficiency of 40%, this would correspond to about 28 dBm of transmitted RF power and 1.7 Watts of total power supplied.

Obviously, as the detailed on-chip structural elements and heat sinking conditions are added to the simulation set-up, the accuracy of the temperature pattern will increase and the heat distribution will correspond more closely to that of a real implementation. Never-the-less, this simplified simulation setup provides valuable temperature gradient information to the designer. Even with this simplified simulation setup, it may be deduced that the temperature difference between the two detectors will reach at least 20º, corresponding to a difference of ~24mV between the two VBE values, which would impair the performances in the two design examples given earlier. Hence, the results suggest that the layout under investigation in this example would not be suitable, and would require different detector locations on the chip.

Use of COMSOL Multiphysics and MATLAB™

Figure 3: Heat pattern simulated with COMSOL Multiphysics.

The simulation described exemplifies the pertinence of an efficient methodology for heat transfer simulation during the development and test of MMICs employing heat-sensitive circuit blocks. The methodology should allow evaluating and optimizing this type of heat distribution starting from a simplified representation of the chip geometry and its structural elements, and with the option of progressively including various structural elements towards a more accurate physical representation of the chip. It also should allow optimizing the physical location of various building blocks and structural elements on the chip, without necessarily imposing the use of complex chip layout design tools.

A development flow was suggested to implement the methodology described above, using MATLAB (The MathWorks) in conjunction with COMSOL Multiphysics. Starting from the chip electrical schematic or the complete die layout, basic electronic blocks (such as transistor arrays, capacitor plates, and other active components) represented in a software format are created using foundry data that can be generic and modulated for a specific foundry. Once these blocks are created, a basic chip structure is created as a generic template in codes, and converted to the format that is readable by MATLAB. The building blocks in this template will have some variability for design parameters such as the location of different transistor cells, distance between transistors, die thickness, location of passive elements that have predominant effects on EM coupling and heat transfer, heat sinking characteristics, and others.

The designer may be involved in the creation of the templates to allow some level of interfacing to the process, with the option of keeping selected foundry proprietary information inaccessible. The designer may also perform theoretical analyses at the subsystem level with MATLAB functions as a function of the EM and heat transfer results simulated by COMSOL. The designer may then export the parameterized chip physical description into COMSOL Multiphysics. With COMSOL, the electromagnetic (EM) and heat transfer (HT) results can be obtained, and the iterative analysis can be performed in an efficient way.

This article was written by Dacian Roman, Anas Alazzam, and Ion Stiharu of Concordia University, Montreal, Quebec, Canada; and Andrei Dulipovici, Vahé Nerguizian, and Nicolas Constantin of École de technologie supérieure, Montreal, Quebec, Canada. This article was originally presented at the 2009 COMSOL Conference in Boston, MA. Visit  to view the full presentation.

RF & Microwave Technology Magazine

This article first appeared in the February, 2010 issue of RF & Microwave Technology Magazine.

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