Developing smart antennas for jam-resistant cognitive or software-defined radio systems entails a number of challenging issues. Researchers at the University of Texas are investigating methods to locate jamming signals and then take evasive action to maintain a communication link. Their work involves the use of large arrays of miniaturized, tunable antennas and adaptive filters to protect the system. The goal is to design a resilient communication system resistant to jamming signals in a wide spectrum of frequencies.
For the implementation of such a novel jamming-resistant adaptive radio system at the proof-of-concept level, a flexible yet powerful real-time architecture is needed. It is critical that the RF front end of the system is integrated with inline signal processing at the hardware level, and that the processing unit is powerful enough to analyze and react to jamming signals in real time.
A modular architecture from National Instruments (NI, Austin, TX) was proposed that incorporates multi-core CPUs, graphics processing units (GPUs), field-programmable gate array (FPGA) technology, and parallel software architectures that provide real-time, high-performance computing capabilities for RF communication systems. The proposed system supports a wide spectrum of standards including Wi-Fi, WiMAX, GPS, RFID, ZigBee, GSM/EDGE, Bluetooth, GPS, and WCDMA, as well as custom communication protocols and new ones such as Long-Term Evolution (LTE) and LTEAdvanced (LTE-A). Multiple protocol layers — from the physical layer (PHY), Media Access Control (MAC), and up—can be implemented on the FPGA, multicore CPU, GPU, or a combination of the three. This multi-layer approach at the hardware level (FPGA-based) provides the flexibility and reconfigurability required for the proposed system.
The proposed proof-of-concept testbed includes a real-time 4-channel/ phase-coherent MIMO system or beamformer, a software-defined radio (SDR), cognitive radio (CR) subsystem, and a numerical/computational subsystem. The 4-channel phase-coherent MIMO/ beamforming subsystem provides tight synchronization with
This SDR/CR subsystem includes three similar nodes, each one with the same configuration. One of these nodes can be combined with the numerical/computational subsystem as a cognitive radio module. The other two nodes can be part of the SDR subsystem and can be used for the implementation of SDR codes directly of FPGAs; each node is based on the NI FlexRIO boards, which are highly reconfigurable using NI LabVIEW FPGA. Each chassis includes four FlexRIO boards, each of which has two main components: one back-end (PXIe-7965R FPGA-based) board, and one front-end module (NI 5781).
The numerical/computational subsystem is designed to execute advanced communication algorithms and perform non-real-time functions, logging, large floating-point numerical computations, and enhanced visualization. This subsystem would be integrated with the other two subsystems via Gigabit Ethernet. This subsystem consists of two NI 8353 multicore CPUs in a 1U form factor integrated with one nVIDIA® Tesla™ S1070 GPU computing system that includes four T10 GPUs. This subsystem is designed to respond to highly demanding computational tasks, and as a co-processor for the PXIe controller in the Phase-Coherent 4 x 4 MIMO and SDR/CR subsystems. The GPUs are programmed using the NI LabVIEW GPU computing framework. At the hardware level, access to four nVIDIA® T10 processors via a Tesla™ S1070 computing system offers a theoretical maximum of 4 TFLOPS on single-precision data that, in practice, could yield 400 GFLOPS or better performance. The NI 8353 multi-core computers are designed for high-performance applications and are fully programmable with NI LabVIEW.
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