Innovative Integration (Simi Valley, CA) has introduced the X6-RX, a flexible receiver that integrates IF digitizing with signal processing on an XMC IO module. The module provides up to 24 configurable receiver channels with a Xilinx Virtex-6 FPGA signal processing core, and a high-performance PCI Express/PCI host interface. IF recorders can log both digitized raw data and baseband channels in real-time, sustaining rates over 2 GB/s. It features four, 16-bit 130 MSPS A/Ds plus a dual digital downconverter (DDC) ASIC. IF frequencies of up to 300 MHz are supported. The sample clock is sourced from either a low-jitter PLL or external input. Multiple cards can be synchronized for sampling and downconversion.

A Xilinx Virtex-6 SX315T, with 4 banks of 128MB DDR2 RAM, provides a DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory, and host interface with the FPGA enables real-time signal processing at high rates. The DDC ASICs, connected directly to the FPGA, provide up to 24 narrowband or 8 wideband channels, with input from any A/D channel. Each DDC channel performs complex or real downconversion, with flexible controls for mixing, filtering, decimation, output formats, and data rates. Channels can be synchronized to support beam forming or frequency-hopped systems.

The X6 modules use less than 10W for typical operation. VITA 20 conduction cooling is used in conjunction with a heat-spreader/sink to provide effective thermal management. Multiple ruggedization levels for wide-temperature operation and conformal coating are supported. The FPGA logic can be fully customized using VHDL and Work Logic toolset. The MATLAB MATLAB using the Frame BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx SystemGenerator. IP cores for DDC, demodulation, and FFT are available.

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This article first appeared in the February, 2011 issue of Embedded Technology Magazine.

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