Effects of Differing Carbon Nanotube Field-Effect Transistor Architectures

Army Research Laboratory, Adelphi, Maryland

Understanding the differing methods and materials that can be used for producing carbon nanotube (CNT)- based electronic components means an informed use of materials and architectures can unleash the potential of carbon nanotube field-effect transistors (CNTFETs) for a wide array of future electronic applications.

In this innovation, single-walled carbon nanotube field-effect transistors (SWCNTFETs) were fabricated with varying device architectures. Variations on the standard back-gated architecture included varying the gate oxide material and thickness, changing source and drain contact metallization, suspending the carbon nanotubes to minimize interaction with the gate oxide, and fabricating a top-gated architecture employing a thin layer of aluminum oxide (Al₂O₃) as the gate oxide. Devices were characterized and compared to each other based on the CNTFET properties of noise, hysteresis, sub-threshold slope, and threshold voltage. Results show that some properties of the CNTFET, such as hysteresis and noise, can be modified; other properties, however, are intrinsic to the CNT.

Top-Gated CNTFETS (a), with interdigitatedsource/drain (lower) and gate (upper) electrodes.The source/drain gaps have unwanted CNTs,which are not overlapped by the gate. (b) Opticalmicroscope image of patterned resist for theselected removal of CNTs that are outside of theelectrode overlap area.

CNTFET device architecture has been shown to affect the properties of CNTFETs, which includes the IS max, noise, and hysteresis. Other properties, such as the metallic or semiconducting nature of these devices, determined by tube chirality (the orientation of the carbon atom lattice in the nanotube), as well as sub-threshold slope, are not greatly affected by device architectures. An appropriate choice of contact metallization, annealing conditions, and CNT density can all increase IS max. While IS min cannot be similarly controlled due to the mixture of semiconducting and metallic tubes as-grown or asdeposited, good on/off ratios can be achieved by burning off the metallic tubes.

Annealing and the choice of gate dielectric were found to affect the device noise and the SNR. Hysteresis was shown to be a property of the CNTFET that can be, for the most part, eliminated with appropriate device geometry, such as a top-gate architecture that provides environmental passivation. This will be advantageous for electronic applications, while greater hysteresis, due to environmental exposure, may indicate a device architecture that is well suited to chemical sensing applications. While a single device architecture will not be optimum for all applications, there are a number of variables that can be tuned to optimize these devices for a given application.

This work was done by Andrew M. Dorsey and Matthew H. Ervin of the Army Research Laboratory. For more information, download the Technical Support Package (free white paper) at www.defensetechbriefs.com/tsp under the Electronics/Computers cate gory. ARL-0090