Applying Reconfigurable Computing to Acoustic Sensors

There is growing interest in the U.S. Armed Forces in the development of microsensor systems that are easily deployed and that support reconnaissance, surveillance, and target acquisition operations. Such systems contain sensors, signal conditioning and processing subsystems, a radio link, and a power source. The role of microsensors is to autonomously detect, classify, and localize targets of interest in a variety of environments. It is generally thought that a number of different sensor types (acoustic, seismic, magnetic, and imaging) may be used to provide orthogonal features to aid in this detection, classification, and localization. These systems must be small (hand-carried), light (100s of grams), inexpensive (less than $200), easily deployable, and have a long operating life.

Figure 1. The FPGA-DSP combination.

In most instances, power consumption (and therefore system lifespan) is a key consideration. Communication bandwidth is often limited by such power constraints, so the amount of data that can be transmitted is minimal. In addition, limiting the amount of data transmission helps the microsensor avoid detection in instances where that is a concern. Communication is the largest consumer of battery power; therefore, much of the signal processing needed to implement the desired functionality must be performed within the previously mentioned size, power, and weight constraints of the microsensor itself to limit the amount of raw data transmitted and to maximize the amount of information. While these requirements highly constrain the microsensor components chosen, at the same time, they demand extremely high computational performance.

Finally, flexibility of the processing fabric is crucial to implement emerging algorithms and support a wide range of sensors and scenarios. Candidates for microsensor processing include application- specific integrated circuit (ASIC) technology, general-purpose processors (GPPs), and field-programmable gate arrays (FPGAs). Although ASIC technology can address the performance, power, and cost issues, an ASIC solution is fixed, requiring a unique design for each sensor type or a large ASIC that can support a finite number of preexisting sensors.

GPPs, which include both conventional CPUs and digital signal processors (DSPs), are more attractive than ASICs for a number of reasons. First, they provide flexibility to make changes, even after deployment. Second, they are driven by the commercial market and readily take advantage of new semiconductor processes. Third, they are standard parts and thus are marketed in large volumes, keeping costs of parts down. However, the most popular processors are not necessarily in the required power regime and are not well suited for DSP. The performance of any GPP is limited by the computational resources it provides. Finally, in a GPP, power cannot be reduced by controlling the number of gates or the number of gates switching simultaneously.

In small to moderate production quantities, typical of many military systems, FPGAs are almost always more cost effective than ASICs.

Common Architecture for Microsensors

The development of a standard architecture that supports a wide range of applications would reduce unit costs through higher volumes than are found in today’s custom microsensor systems. Experience has shown that FPGAs are well-suited to the development of deeply pipelined datapath applications typical in signal processing, while GPPs are better suited to system control and communication applications.

The architecture we have developed (see Figure 1) allows the FPGA to act as a reprogrammable preprocessor or coprocessor to a GPP. The FPGA does most of the computationally complex pieces of the algorithm while the GPP is lightly loaded, performing control, communications, and housekeeping tasks. A by-product of this is that a simple lowpower GPP can be used.

We developed CAμS (pronounced “cause”), the Common Architecture for Microsensors. The CAμS processing architecture consists of a data acquisition module, DSP module, and FPGA module. CAμS is independent of a specific I/O technology and provides a large amount of user-defined digital I/O for interconnection to a variety of devices. Although we include a radio, the architecture can easily accommodate different radio technologies. The software and hardware can be programmed (configured) through a serial port with support to change the nonvolatile memory in situ. This nonvolatile memory is able to store four separate system configurations (DSP and FPGA configurations).

The system is partitioned into sensor head, signal conditioning and processing, communication, and battery. An obvious system configuration is to integrate the processing, communication, and battery into a base unit, and the user could then attach sensor heads. Such a system could even act as a gateway for, or a manager of, a distributed sensor network. Our proof-of-concept system is based on a commercially available DSP and FPGA (the Motorola 56307 and the Xilinx Virtex XCV1000) in a standard PC-104 form factor. The system consists of either four or five cards: the DSP card, a power card, a data acquisition card, and one or two FPGA cards, depending on the application at hand.

Connections between the FPGA and the other boards allow the FPGA to control the data acquisition module and to interrupt the DSP. Additionally, the FPGA is connected to the DSP bus, making it possible to memory map FPGA resources into the DSP address space.

Acoustic Sensor for Target Detection and Bearing Estimation

Figure 2. The circular acoustic sensor array.

The first CAμS application developed is an acoustic sensor system for ground-vehicle detection and bearing estimation. The sensor array is formed by a collection of omnidirectional microphones, each providing 360-degree field-of-view coverage. The sensors are placed on or near the ground in a certain geometric shape to conform the array. The microphone array designed for application consists of seven microphones, six in an 8-footdiameter circle and one in the center (see Figure 2).

The signals received at each of the microphones are sampled at 1 kHz and the resulting data are multiplied by a windowing function. After a corner turn of the data, seven 1,024-point fast Fourier transforms (FFTs) are performed. A detection algorithm is then run on the FFT output magnitudes to identify possible targets. This is done in two stages. First, a peak picking algorithm estimates the noise floor and high-power frequency bins are selected with a threshold determined from that noise floor.

Harmonic line analysis is performed to find groups of frequency bins that form a harmonic relationship. Groups containing enough frequency components are declared to be targets. In the second stage, beamforming is performed on the raw data at the target’s frequencies to determine exact target bearings. Finally, a tracking filter is applied to reduce the number of false reports and provide a lock on the target’s bearing, providing lines-of-bearing (LOB) updates once every second.

This entire computation could be done on either the CAμS DSP or the CAμS FPGA alone. An evaluation of the characteristics of each subcomputation because of power consumption and throughput requirements, however, argues for a partitioning of the problem across both the DSP and FPGA. The main consideration is power. The DSP and associated static random access memory (SRAM) consume approximately 40 mW when in standby mode, 510 mW at 256 kHz, and 1500 mW at 30 MHz. In contrast, the FPGA has a quiescent power of 200 mW, with additional power being a function of the design’s gate count, operating frequency, and number of onboard memories used by the FPGA. Three options to use these two modules for this computation exist: (1) eliminate the FPGA, (2) use both the DSP and FPGA, and (3) eliminate the DSP.

In its final form, this application was implemented via option (2) and consumed a total of 482 mW, including all system modules except the radio. The DSP was run at a high clock rate, and the FPGA clock rate was 256 kHz. From this, one can see that eliminating the DSP and its 43 mW of power as in option (3) would have given a 9-percent overall power reduction at best. This example shows that microsensor applications are an area where FPGAs can be used not only to increase system capabilities but also to significantly reduce power consumption.

A number of factors are combining to make FPGAs a technology enabler for future microsensor systems. Limited communications bandwidth and the high power associated with communications are forcing the migration of signal processing to the sensor head. The superior performance/power characteristics of FPGAs for many signal conditioning and processing algorithms, coupled with a desire to support unattended sensor lifespans of up to a year, points to FPGAs as the technology of choice for these computations.

Future work will focus on adapting CAμS for use with additional sensors and on miniaturizing the CAμS architecture. In this upcoming microsensor system, the FPGA-based processor will be capable of supporting magnetic, acoustic, seismic, and imaging (day or infrared (IR)) sensors all in the same package. The FPGA will have to be reconfigured in real time to facilitate such a sensor suite.

The context-switching reconfigurable computing (CSRC) technology now being developed by Sanders extends commercially available FPGA devices to include high-speed changes between a number of programmed functions without the need for additional FPGAs. Each configuration, referred to as a context, in a CSRC FPGA has the functionality similar to that of many commercially available FPGAs. The context switching can occur at significantly higher speeds than the rate at which current FPGA technology can reconfigure. In addition, unlike commercial FPGAs, where reprogramming destroys any resident data, the CSRC FPGA can share data between contexts.

The true potential of context switching requires a paradigm shift in algorithm implementation. The capabilities of the CSRC architecture, which extend dynamic reconfiguration to context switching, can provide improved implementations of signal processing algorithms over those currently available through commercial FPGAs. The inherent ability of CSRC to quickly perform different tasks and share results among different configurations allows one to approach algorithms from a different perspective, enabling mathematical implementations previously inconceivable without context switching.

This article was written by Andree Filipov of the U.S. Army Research Laboratory in Adelphi, MD, and Mark Falco of Sanders, part of BAE Systems Electronics & Integrated Solutions (E&IS), in Nashua, NH. For more information, visit BAE Systems E&IS here .