Next-generation radar applications will drive performance demands that will have architectural implications for radar computing and electronics. Advanced multi-function radar (MFR) systems, which will be deployed in harsh and demanding environmental conditions inside unmanned aerial vehicles (UAVs), manned aircraft, and ship- and ground-based radar systems must simultaneously provide multi-mode search, multi-target tracking, synthetic aperture radar (SAR) imaging, and space time adaptive processing (STAP). Both the performance and ruggedization requirements make it challenging to service MFR applications using yesterday's commercial- off-the-shelf (COTS) technologies.
COTS solutions based on open standards are now meeting these requirements. The blend of massive fabric bandwidth, field programmable gate array (FPGA) processing power, PowerPC high-compute-density farms, and standards-based I/O housed in a conduction-cooled system address the simultaneous requirements of performance within an enclosure that can withstand the extremely hazardous field conditions found in deployed radar. VPXREDI, a next-generation standard that combines the VITA 46 and VITA 48 standards with the RapidIO open-standard switched fabric, significantly advances the robustness and performance of COTS sensor computing.
Mission-Critical System Challenges
Engineering and integrating highly reliable mission-critical systems that provide the deployed warrior with radar and navigation capabilities required for very challenging missions is key. A typical leading-edge problem involves minimizing the enemy's broadband jamming efforts or eliminating ground or sea clutter located at arbitrary or unknown locations. The solution is to compute and track the angular locations of the jammers or clutter by appropriately processing the received signals, and then adaptively generating a time- and frequency varying antenna pattern that places angular pattern nulls at the computed jammer location(s). Figure 1 shows an example of front-end data acquisition to back-end processing and control.
Actual implementation depends upon a number of basic capabilities:
- Multi-element antenna (8 to 100 elements),
- Separate receiver channel and A/D for each element/channel,
- Efficient mapping of dedicated hardware for the pulse compression algorithms on field programmable gate array (FPGA) modules,
- Tightly coupled fabric connectivity for corner-turning operations, and
- Data exchanges with the high-compute density processing modules for the final STAP and data processing.
The STAP application's I/O distribution described above entails more than 10 gigabytes per second of bisection bandwidth within a system and gigaflops of processing power. The two most challenging areas of the problem (Figures 2 and 3) are the real-time receive beam-forming computational rates at up to 40 MHz and the adaptive beam-forming weight computations at a rate of 100 Hz to 1,000 Hz.
Open-Standard COTS Systems
By providing a modular COTS system based on open standards, the exceptionally demanding I/O in gigabytes per second and processing requirements of 10 to 100 GFLOPS for STAP and SAR algorithms can be met by combining the front-end functionality of high-speed microwave tuners and high-speed A/Ds in the speed range of 3 GHz or greater. FPGAs and PowerPC resource modules also are used for dedicated high-speed computations such as the pulse compression operations for high-range resolution; effective short pulse response derived from the long, high-energy transmitted pulses; and lastly, returns. The complete processing chain operating on the three-dimensional (3D) radar data cube is shown in Figure 4.
A system host carrier module is required to orchestrate and synchronize the radar receiver/exciter and data collection control, and to prosecute the I/O distribution among the various FPGAs for signal conditioning and general-purpose processors for data processing and image formation. The switching fabric connects all of the modular components in the system, enabling the quick and efficient exchange of data between processors, and enabling the implementation of corner-turning for the SAR algorithm and all-to-all data exchanges at the maximum data rates of the packet switched serial RapidIO fabric in the aggregate range of 16 Gigabytes per second or greater as a measure of systemwide bisection bandwidth.
To meet algorithm challenges such as the STAP spatial processing algorithm, a modular hardware architecture based on a standard form factor and a standard switched I/O fabric is required. The focus of the future STAP-capable radar system solution described below will be implemented using a VPX-REDI (VITA 46 and 48) 6U format standard and a serial RapidIO switched fabric. The new system design provides the necessary compute power and I/O bandwidth to fully implement the STAP and SAR algorithms mentioned above. Mercury Computer Systems' PowerStream 6600 VPX-REDI rugged computer system is an example of such a system. It can achieve more than 34 Gigabytes per second of system-wide RapidIO fabric throughput. Its 16 modules can house 64 PowerPC processors or alternatively 21 user-programmable Xilinx Virtex 4 FPGAs in a conduction-cooled format made possible by the VPX-REDI form factor.
The corner turn shown in Figure 4 is one of the greatest challenges facing radar processing systems. VPX-REDI introduces a new module format based on a new set of high-speed differential signaling connectors. The adoption of a new connector set in the VPX-REDI standard paves the way for higher-speed signaling, greater power budgets, and an enormous increase in I/O capabilities. VPX-REDI systems can achieve hundreds of Gigabytes per second of system throughput using high-speed serial fabric interconnects.
A key difference in the architecture of VPX-REDI is its ability to support an expansive, full-mesh compute fabric topology through an increased number of serial fabric links on each module. The full mesh provides all-to-all connectivity without requiring a dedicated fabric- switching slot, as is the general case in other form factor architectures, namely VXS (VITA 41). There also is support for an interconnected common set of building block technologies including standard I/O mezzanine cards, PowerPC processors, FPGAs, and the RapidIO fabric.
New radar systems require two-level maintenance (2LM) when a failure occurs and end users swap out individual electronics modules in the field. VPX-REDI provides the electrical and mechanical infrastructure that protects individual electronics modules from electrostatic discharge (ESD) when they are being handled by personnel. This includes specially designed backplane connectors, carefully placed GND signals to sink excess current, and robust module covers.
Mobile applications impose certain constraints on computing. Ground mobile vehicles can operate in regions of extreme temperature and where the air is dusty, or worse, chemically contaminated. This environment precludes the use of air convection cooling. Conduction cooling provides passive means by which heat can be conducted for the card to the outside wall of the chassis. The chassis wall can be cooled with a fan, but this has none of the implied problems of blowing air directly across the board. The conduction-cooling board exoskeleton also provides reinforcement for high shock and vibration applications.
Airborne applications tend to prefer air cooling since it is lighter in terms of weight than conduction cooling. However, tactical fighters that achieve heights of 70,000 feet may have difficulty cooling electronics at low pressure. Despite the disadvantage of weight, these types of airborne applications also choose to make use of conduction cooling.
The radar compute subsystem addressing these requirements comprises a VPX-REDI chassis and three basic processing modules connected via a serial RapidIO backplane fabric and other backplane interconnects. The system's conduction-cooled modules include an I/O mezzanine carrier, a PowerPC signal processing card, and an FPGA compute resource card. The VPX-REDI backplane provides a means for each slot to transfer data to any of 16 other slots via a RapidIO fabric interface without the use of a central switch card.
The I/O carrier module is a smart (processor-based) I/O mezzanine carrier that also serves as the scalar data and control processor for the radar receiver/ exciter. It contains two MPC8548 processors that can serve as application processors or I/O engines servicing respective mezzanine card sites. The two mezzanine cards support PMC-X or XMC interfaces, providing systems integrators with a wide and established ecosystem of option cards that may be incorporated.
The high-compute-density (HCD) module is a quad PowerPC AltiVec processor resource board. Each MPC7448 processor on the HDC operates at 1.4 GHz with a 400-MHz DDR2 memory interface. Each HCD module contains four PowerPC compute nodes (CNs) connected by a low-latency RapidIO crossbar to implement the network of fully connected floating point processors necessary to provide the GFLOPS of processing power for SAR and STAP algorithms.
The FPGA resource board houses three user-programmable Xilinx Virtex-4 FPGAs and can be delivered with an FPGA Developer's Kit (FDK). This kit puts the basic building blocks needed for system integration at the fingertips of developers: RapidIO fabric and serial FPDP bridge end-point IP, data movement functionality, memory controllers, etc.
Multi-function radars present enormous challenges for system integrators, but COTS solutions based on open standards are now meeting them. The combination of massive fabric bandwidth, FPGA processing power, PowerPC high-compute-density farms, and standards based I/O housed in a conduction cooled system can address the simultaneous requirements of performance within an enclosure that can face the extremely hazardous field conditions found in deployed radar.
This article was written by James Meyer, Senior Systems Applications Engineer at Mercury Computer Systems, Chemlsford, MA. For more information, Click Here .