Next-generation radar applications will drive performance demands that will have architectural implications for radar computing and electronics. Advanced multi-function radar (MFR) systems, which will be deployed in harsh and demanding environmental conditions inside unmanned aerial vehicles (UAVs), manned aircraft, and ship- and ground-based radar systems must simultaneously provide multi-mode search, multi-target tracking, synthetic aperture radar (SAR) imaging, and space time adaptive processing (STAP). Both the performance and ruggedization requirements make it challenging to service MFR applications using yesterday's commercial- off-the-shelf (COTS) technologies.

COTS solutions based on open standards are now meeting these requirements. The blend of massive fabric bandwidth, field programmable gate array (FPGA) processing power, PowerPC high-compute-density farms, and standards-based I/O housed in a conduction-cooled system address the simultaneous requirements of performance within an enclosure that can withstand the extremely hazardous field conditions found in deployed radar. VPXREDI, a next-generation standard that combines the VITA 46 and VITA 48 standards with the RapidIO open-standard switched fabric, significantly advances the robustness and performance of COTS sensor computing.

Figure 1. Complete data acquisition and signal processing applied technology chain.

Mission-Critical System Challenges

Engineering and integrating highly reliable mission-critical systems that provide the deployed warrior with radar and navigation capabilities required for very challenging missions is key. A typical leading-edge problem involves minimizing the enemy's broadband jamming efforts or eliminating ground or sea clutter located at arbitrary or unknown locations. The solution is to compute and track the angular locations of the jammers or clutter by appropriately processing the received signals, and then adaptively generating a time- and frequency varying antenna pattern that places angular pattern nulls at the computed jammer location(s). Figure 1 shows an example of front-end data acquisition to back-end processing and control.

Figure 2. Computationally intensive beam-forming requirements for a single pulse return data set.

Actual implementation depends upon a number of basic capabilities:

  • Multi-element antenna (8 to 100 elements),
  • Separate receiver channel and A/D for each element/channel,
  • Efficient mapping of dedicated hardware for the pulse compression algorithms on field programmable gate array (FPGA) modules,
  • Tightly coupled fabric connectivity for corner-turning operations, and
  • Data exchanges with the high-compute density processing modules for the final STAP and data processing.

The STAP application's I/O distribution described above entails more than 10 gigabytes per second of bisection bandwidth within a system and gigaflops of processing power. The two most challenging areas of the problem (Figures 2 and 3) are the real-time receive beam-forming computational rates at up to 40 MHz and the adaptive beam-forming weight computations at a rate of 100 Hz to 1,000 Hz.

Open-Standard COTS Systems

Figure 3. Application of adaptive weighting techniques to pattern null interference and jamming.

By providing a modular COTS system based on open standards, the exceptionally demanding I/O in gigabytes per second and processing requirements of 10 to 100 GFLOPS for STAP and SAR algorithms can be met by combining the front-end functionality of high-speed microwave tuners and high-speed A/Ds in the speed range of 3 GHz or greater. FPGAs and PowerPC resource modules also are used for dedicated high-speed computations such as the pulse compression operations for high-range resolution; effective short pulse response derived from the long, high-energy transmitted pulses; and lastly, returns. The complete processing chain operating on the three-dimensional (3D) radar data cube is shown in Figure 4.

A system host carrier module is required to orchestrate and synchronize the radar receiver/exciter and data collection control, and to prosecute the I/O distribution among the various FPGAs for signal conditioning and general-purpose processors for data processing and image formation. The switching fabric connects all of the modular components in the system, enabling the quick and efficient exchange of data between processors, and enabling the implementation of corner-turning for the SAR algorithm and all-to-all data exchanges at the maximum data rates of the packet switched serial RapidIO fabric in the aggregate range of 16 Gigabytes per second or greater as a measure of systemwide bisection bandwidth.