Satellite and spacecraft system designers have a few different options when selecting field programmable gate arrays (FPGA) semiconductors. One FPGA option is commercial off-the-shelf (COTS) components that reduce component unit cost and lead time, but they are generally not reliable enough, must be up-screened (which increases cost and engineering resources), and require soft and hard Triple Modular Redundancy (TMR) to mitigate radiation effects in space.

In missions where failure is not an option, designers typically choose higher-cost FPGAs that are radiation-hardened by design (RHBD). These are already screened and qualified to Qualified Manufacturers List (QML) Class Q and V standards. QML Class V is the highest qualification standard for space semiconductors. Manned and safety-critical missions rely on QML-V components, to mitigate the risk of failure.

Designers whose systems must meet the increasing need for a challenging combination of higher performance and greater on-board data processing and high-speed communications capabilities in space also rely on these radiation-tolerant RT FPGAs to provide a solution that is radiation tolerant by design, backed by its manufacturer's space flight heritage and expertise, and undergo QML Class V testing. This article will look at the different FPGA technologies that are available for space applications, and the process for developing the components.

Radiation Effects in Space

Flash and SONOS-based FPGAs are immune to SEUs in the configuration memory.

RT FPGAs are needed because COTS components are not immune to the various radiation effects in space and that can degrade the performance of an integrated circuit or cause it to fail. One of these radiation effects is total ionizing dose (TID), which is caused by radiation due to charged particles and gamma rays in space. This radiation deposits energy by causing ionization in the material. The ionization can change the charge excitation, charge transport, bonding, and decomposition properties of the material. This negatively affects the device parameters.

TID is the cumulative ionizing radiation that an electronic device receives over a specified period, usually the mission time. The damage is dependent on the amount of radiation and is expressed in radiation absorbed dose (RAD). Depending on the radiation tolerance for TID, a device may experience functional or parametric failures. Among the common parameters affected by TID radiation in FPGAs is an increase in propagation delay which decreases device performance. Another failure mechanism is increased leakage current after a high TID exposure.

The other type of radiation effect is single-event effects (SEEs). These are instantaneous upsets, transients, or permanent damage due to particle radiation such as protons, heavy ions, and alpha particles that can strike sensitive regions of the transistor, causing various failures. SEEs come in different forms including Single Event Upsets (SEUs), which occur when high-energy ionizing particles such as heavy ions, alpha particles or protons irradiate a circuit or pass through an integrated circuit. This results in a disruption in the system logic.

Also troublesome is a Single Event Latch-Up (SEL), which is a condition that causes loss of device functionality due to a single-event-induced high current state. An SEL may or may not be destructive. In a destructive latch-up event the current will not recover to the nominal value. In a non-destructive latch-up event the high-level current will return to the nominal value after power-cycling the FPGA.

Comparing FPGA Technologies

There are four basic types of FPGAs:

SRAM-based FPGAs

SRAM-based FPGAs store logic cells configuration data in the static memory. SRAM is volatile and can't retain the device configuration without power. Instead, the FPGAs must be programmed upon power-up. SRAM-based technology tends to consume more power and be more sensitive to radiation.

Flash-based FPGAs

Reprogrammable flash-based FPGAs use flash as a primary resource for configuration memory. Flash technology is immune to SEU, eliminating the threat of radiation-induced upsets in the configuration memory of the FPGA. RTG4 Flash-based FPGAs use up to 50 percent less power compared to SRAM-based FPGAs. Flash technology simplifies the design in multiple ways, as there is no need for external memory, redundancy, or continuous configuration monitoring. It also eliminates the need for a heat sink, reducing the size and weight of the designs while reducing power consumption, which can be especially important if an electronic module is powered with solar panels.


An example is the Microchip RT PolarFire FPGA, which offers radiation performance with characterized radiation data, low power, SEU configuration immunity, and high-reliability components with a path to QML-V qualification. These FPGAs are developed on a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile (NV) technology on a 28nm technology node.

The performance of 28nm and earlier 65nm technologies has been compared by measuring the propagation delay of an inverter. These tests show that 28nm SONOS technology offers 2.5 times higher performance than 65nm flash-technology. These SONOS-Based FPGAs also have outstanding radiation performance and SEU immunity, while offering a low-power solution. With a path to QML-V qualification, SONOS-based FPGAs are ideal in applications that require high-speed signal processing.

The accompanying figure shows how flash and SONOS-based FPGAs are architected to provide SEU immunity.

Antifuse-based FPGAs

Antifuse-based FPGAs are programmed once, which limits a key re-programmability advantage as compared to Flash and SONOS-based FPGAs. Antifuses do not conduct current initially but are burned to conduct current (the antifuse behavior is the opposite to the behavior of a fuse). Antifuse technology is very robust against radiation effects.

How RT FPGAs are Developed

RT FPGAs are developed on process technologies that have excellent radiation TID performance. They can be RHBD, with flip-flops that have built-in TMR at the circuit level. TMR deployed in software, also known as soft TMR, can be implemented if the TMR has not already been implemented at the silicon level. After the silicon is developed, RT FPGAs go through a stringent qualification.

For devices to be qualified to the highest standard, they must adhere to the MIL-PRF-38535 standard that was released by the Department of Defense, which created consistent qualification, testing, and reliability standards for military and space ICs. MIL-PRF-38535 defines requirements for IC manufacturers if they wish to be listed on the QML by the Defense Logistics Agency (DLA).

Another aspect of product development is characterizing SEE performance, which does not change from wafer lot to wafer lot if the silicon design is the same. After freezing the design, FPGA manufacturers can start the SEE characterization process. Once the device is in production, no additional SEE performance testing is needed as long as there have been no changes to the design and the component has been fully characterized.

Some process technologies may have TID performance that varies across wafers from lot to lot. As a result, TID performance testing must be performed in production, on a wafer lot basis, to guarantee a device will meet its target TID level specification (25 krad, 100 krad, 300 krad).

RT FPGAs' Impact on Spacecraft Design

The latest RT FPGAs offer numerous advantages that create opportunities for simplifying these designs while significantly improving the capability for on-board data processing. To meet these needs, RT FPGA technology nodes are shrinking to offer higher performance and higher-speed signal processing with more memory and DSP capabilities.

RT FPGAs also offer other key advantages including re-programmability and faster development time compared to an ASIC. Typically, FPGAs are not reprogrammed once they are flying in space, but this is an option as designs become more complicated, assuming that system designers follow guidelines and carefully evaluate the success rate and risks associated with on-orbit reprogramming.

This article was written by Julian Di Matteo, Senior Product Marketing Engineer, Space and Aviation, Microchip Technology (Chandler, AZ). For more information, visit here .

Aerospace & Defense Technology Magazine

This article first appeared in the September, 2020 issue of Aerospace & Defense Technology Magazine.

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