Many applications can benefit from pushing software radio functions up the mast to the antenna as a viable alternative to traditional rack-mounted receiver systems. New technology offers engineers of Software Defined Radio (SDR) systems diverse opportunities to apply digital signal processing (DSP) much closer to the antenna than ever before. Various strategies include the latest wideband data converters, monolithic receiver chips, compact RF tuners, and remote receiver modules using gigabit serial interfaces. Each approach presents benefits and tradeoffs that must be considered in choosing the optimal solution for a given application.

Strategies for the Latest Wideband Data Converters

With the emergence of monolithic A/D converters capable of sampling rates of 5 GHz and higher, engineers can now directly digitize analog RF signals covering a frequency span of more than 2 GHz. This allows the capture of wideband communications and radar signals in a single data stream, eliminating the complexity of splitting a given band into parallel adjacent sub-bands, and the inevitability of input signals straddling them. While these new converters appear to simplify software radio architectures, they also impose many limitations and tradeoffs.

RF signals from the antenna must first be amplified, filtered, and possibly down-converted in frequency to match the input voltage range and usable input bandwidth of the A/D converter. Optimal amplifier gain boosts the strongest signal to the full-scale input range of the A/D. Further amplification to boost weaker in-band signals will cause overloading the A/D, which destroys the signal integrity for all signals. Thus, even one strong interferer will reduce the achievable dynamic range for weaker signals. This significant tradeoff occurs whenever a single A/D is used to handle a large number of signal types in a wide frequency span. To make matters worse, as sampling rates increase, A/D converters deliver lower Effective Number of Bits (ENOB) ratings. For example, a 5-GSample/sec 10-bit A/D converter may only deliver an ENOB of 7.6 bits.

Also, filtering is imperative to eliminate all energy outside the frequency span of interest. Otherwise, aliasing will fold out-of-band noise and adjacent signals into the digitized signal stream, degrading signal-to-noise performance and adding spurious signals.

Lastly, A/D data arriving at several GSamples/sec will overload most DSPs. Data de-interleaving hardware is often built into the A/D to help implementation of the electrical interface, but even so, every data sample must somehow be processed, stored, or transferred. The latest families of field-programmable gate arrays (FPGAs) are especially well suited, not only in dealing with these extremely high data interface rates, but also in processing signals in real time.

One product example is the Pentek 71641 3.6-GHz A/D and Digital Down Converter (DDC) XMC module. It features a 12-bit 3.6-GSample/sec A/D converter coupled to a Virtex-6 FPGA. The A/D de-interleaves samples into eight parallel 12-bit streams, delivering samples to the LVDS ports of the FPGA at 450 MSamples/sec each. Inside, eight parallel engines implement a DDC that tunes across the 1.8 GHz input band (Figure 1). It performs frequency translation to baseband and provides digital filtering of the complex baseband output samples. Selectable output bandwidths of 90, 180, or 360 MHz, representing tunable slices of the input spectrum, are delivered to the system through a native PCIe Gen 2 x 8 interface.

Monolithic Receivers

Figure 1. The Pentek 71641 3.6 GHz A/D and Digital Down Converter (DDC) XMC module features a 12-bit 3.6 GSample/sec A/D converter coupled to a Virtex-6 FPGA, which helps deal with extremely high data interface rates and processing signals in real time.
New classes of monolithic silicon receivers offer an impressive integration of diverse RF analog circuitry required to implement a complete software radio tuner front end. These low-cost devices accept input signals directly from the antenna and deliver amplified, translated, and filtered analog baseband outputs suitable for low-speed A/D converters or demodulator chips.

For example, the Maxim MAX2112 targets satellite set-top and VSAT applications including 8PSK modulation and Digital Video Broadcast (DVB-S2) applications. It uses an LNA to boost antenna input signals falling between 925 and 2175 MHz, as well as a programmable gain RF amplifier for 80 dB of overall gain control.

An integrated VCO and programmable fractional-N frequency synthesizer drive a quadrature mixer to tune across the entire input frequency range, downconverting any input signal to I+Q baseband. These baseband signals are band limited with a pair of low-pass filters, programmable from 4 to 40 kHz. This extremely high level of integration on a single chip dramatically reduces the size and cost of the receiver, and is ideal for applications restricted in space, power, weight, and cost or requiring a large number of channels.

However, while these devices work well for applications requiring only modest signal-to-noise ratios like satellite signal interception, they are not suitable for some of the more demanding government and military systems for communications, signal intelligence, and radar.