A dynamically reconfigurable, wideband programmable RF FPGA transceiver will provide reduced lifecycle cost, reduced redesign cost, and service for multiple DoD platforms, while maintaining near-optimal performance for each application.

State-of-the-art RF integrated circuits (ICs) achieve high performance via custom circuit elements with dedicated signal paths for application-specific functions, but long design lead times and non-recurring fabrication costs increase time-to-market for new applications and limit reuse. The key to developing an RF FPGA (radio frequency field-programmable gate array) is to provide RF switching components with very low insertion loss and high isolation that can be integrated with high-performance RF circuits in silicon germanium (SiGe) and gallium nitride (GaN) technologies, and integrating these circuits in a reconfigurable topology to allow an RF FPGA to perform a wide variety of functions.

Figure 1: The 8-port phase change RF switch design.
Key elements of the RF FPGA approach are:

  • Extremely low-loss, high-isolation RF switches using phase change materials (PCM). Multiport RF switch designs (Figure 1) optimize thermal design to improve PCM performance, and integrate arrays of these switches on thermally and electrically optimized substrates.
  • Multiport switch designs with low simulated RF losses of 0.1 - 0.2 dB up to 20 GHz, and 35dB - 60dB isolation between ports, based on measured and extrapolated PCM data. They consume no prime power except for 100-nsec heater pulses during reconfiguration.
  • An architecture that connects these switches in a fully interconnected matrix to allow total flexibility in interconnecting and switching between RF elements and to inputs/outputs.
  • Dynamically RF tuned banks of wideband, high-performance LNAs (low noise amplifiers), mixers, vector modulators, driver amplifiers, and power amplifiers using programmable circuit bias and circuit mission reconfiguration techniques.
  • Development of a family of RF FPGAs that can be configured in a variety of ways: as a standalone RF transceiver, as T/R (transmit receive) elements in an AESA (active electronic scanned array), or as an IF (intermediate frequency) or baseband receiver. Packaging in 12 x 12-mm QFNs (quad-flat no-leads) packages with matched RF I/O for low package insertion loss is used to allow multiple RF FPGAs to be integrated in flexible configurations.
  • Demonstration of the RF FPGA technology against multiple DoD system applications with transition potential to a wide range of DoD systems.

Robust, Low-Loss Switch Technologies

Figure 2: The flexible switch matrix connects RF circuit banks with each other and I/O for a high level of reconfigurability.
To produce an efficient RF FPGA, a compact, low-loss RF switch is the essential technology needed. The phase change RF switches will be used to create a fully interconnected switch matrix (Figure 2). These switches will connect banks of RF components (e.g., LNAs, mixers, filters, vector modulators) on the RF ICs to each other, also allowing routing from any of these circuits to the RF FPGA I/O. The RF switches are fabricated on separate silicon (SiC) wafers, optimized for RF and thermal phase change performance, and then flip-chip-bonded to the RF component IC.

To further minimize RF losses due to the switch matrix, the routing lines between switches are fabricated using high-conductivity metal (such as copper), 50-Ohm transmission lines on low loss dielectric, such as BCB. The transmission lines will be configured as microstrip, with lines over and under the ground plane to provide the isolated RF signal crossover capability required by the fully interconnected matrix. The stackup showing the integration of the RF IC, interconnect matrix, and switches in a QFN package is shown in Figure 3.

High-Performance RF Architecture

The RF FPGA uses a coarse-grained architecture consisting of major functional blocks with reconfigurability both within the blocks and between the blocks. This approach provides higher RF performance than a fine-grained architecture, and has the degree of flexibility needed for a wide range of applications due to the fully connected RF switch matrix.

The receiver FPGA contains banks of LNAs, sub-octave filters for RF filtering, vector modulators for beam steering, down conversion mixers, and digital control. Jazz SiGe is used as the integration platform because the RF performance is very good, digital control and power supply circuits for the phase change heaters can be easily integrated into the same IC, and device fabrication is relatively inexpensive. The number of RF elements and their bandwidths in each bank have been selected to provide the 0.4 to 18 GHz range, based on previous SiGe designs.