The requirements for smaller size, lower weight, and reduced cost in space and defense systems are driving demands for improved power-management solutions. Integrated DCto- DC converters that are designed for hi-rel applications, such as POL buck regulators, offer considerably smaller size and lighter weight than similar multi-chip technologies. The use of a single chip improves reliability issues related to assembly and, with these single- chip POL buck regulators, system designers benefit from improved efficiency and design flexibility.

Figure 1. The complete dielectric isolation between adjacent NMOS and PMOS transistors in UltraCMOS® technology means that latch-up cannot occur, unlike with junction-isolated bulk silicon technology processes.
While defense space systems vary in size, functionality and complexity, radiation immunity is often important. An interruption or failure due to radiation during operation could have detrimental effects. However, due to reductions in government funding, as well as improvements in technology, some defense and aerospace systems designers may choose Commercial Off the Shelf (COTS) components to reduce cost, or simply because a rad-hard equivalent does not exist. UltraCMOS technology-based DC-to-DC POL buck regulators are naturally radiation hardened (rad hard), and can offer a more cost-effective total solution in comparison to other products. These POL buck regulators can also eliminate the need for designers to trade off cost for potential mission failure due to radiation effects.

Rad-hard FPGAs and ASICs are used extensively in defense systems. Powermanagement designers are challenged to meet the increased multi-core operation and faster processing speeds required of these designs. As process technology shifts to lower and tighter tolerances, voltage regulators must supply more power at lower voltages. The benefits offered by UltraCMOS technology fit well into the long-range strategy of many hi-rel defense applications.

Radiation Requirements

The primary radiation concerns in the natural space environment are Total Ionizing Dose (TID), Enhanced Low Dose Rate Sensitivity (ELDRS), and Single Event Effects (SEE). TID degradation or gain drifts of component parameters cause changes to circuit supply and leakage currents, threshold voltages, and propagation times. ELDRS can degrade certain types of bipolar devices more severely at very low dose rates than at higher dose rates. Additionally, the effects from a high-energy particle passing through the active region of a semiconductor can trigger non-destructive effects such as single event upset (SEU), single event functional interrupt (SEFI), and single event transient (SET); or destructive effects such as single event latch-up (SEL), single event gate rupture (SEGR), and single event burnout (SEB). Program missions will determine the level of radiation immunity required.

What Is UltraCMOS® Technology?

Figure 2. Peregrine Semiconductor’s PE9915X rad-hard, integrated Point-of-Load (POL) buck regulator.
UltraCMOS is a patented Silicon-on- Sapphire (SOS) semiconductor pro cess technology that has long been recognized as a technically-superior technology reserved for highly-specialized military projects, among other applications. UltraCMOS technology circuitry is processed on an Ultra-Thin Silicon (UTSi®) layer atop a dielectric sapphire wafer. As a result, variable capacitances in the junction region are eliminated, which improves the transistor’s voltage handling and reduces the overall current drain. Additionally, high-quality passive and RF functions, as well as digital circuitry can be integrated on a single die. This high level of monolithic integration results in a smaller IC, which helps reduce overall design size and the number of external components required. Moreover, because UltraCMOS devices are fabricated in standard high-volume CMOS facilities, products benefit from the reliability, cost effectiveness, high yields, scalability, and integration of CMOS, while achieving peak performance levels.

Another important advantage of UltraCMOS technology to the defense industry is that it is naturally rad hard. For example, SEL is the radiationinduced latch-up of a CMOS logic gate. This can happen when a high-energy particle strikes the parasitic thyristor that is inherent to bulk silicon designs and causes a short circuit from power to ground within the device. This is often catastrophic and results in permanent damage, requiring, at a minimum, a power down to recover. Products created using SOS semiconductor process technology, such as UltraCMOS technology, do not contain the bulk parasitics found in regular CMOS devices, making latch-up impossible (Figure 1).

Bipolar technologies with oxide isolation structures, such as COTS and older DC-to-DC converter designs, suffer from lower dose rates. So far, this has not been an issue with DC-to-DC converters based upon CMOS technology, (Figure 2). Moreover, SOS technology, with its highly-insulating substrate properties, does not use bipolar minority carrier elements, and does not exhibit enhanced low-dose-rate sensitivity.

Integrated Point-of-Load (POL) Buck Regulators

Figure 3. Example of a Distributed Power Architecture (DPA).
With the increase in processing power from digital applications, there is a high demand for smaller power-management devices that provide high load currents at low output voltages, while maintaining high efficiency. POL buck regulators with integrated switches enable a smaller form factor, improved reliability, and flexibility that allow system architects and designers to meet project goals. Several important design tradeoffs and features are available for optimal system performance, including high power efficiency, adjustable output voltage, selectable switching frequency, synchronization, adjustable current threshold, adjustable loop compensation, power-good indicator, supply sequencing, and current-sharing capability.

Distributive Power Management

One of the most critical factors in an FPGA system design is power-management. High-performance signal-processing devices require multiple power supplies that generate different voltages. Usually, a minimum of two voltages are needed to power FPGA–one for the core and one for the I/O supply. Many FPGAs also require a third low-noise, lowripple voltage to provide power to the auxiliary circuits. The FPGA can have current demands of up to tens of amps, depending upon the clock frequency and the number of gates being used.

The Distributed Power Architecture (DPA) is often the power system of choice to ensure optimal system performance when supplying high-performance digital loads. The traditional single, centralized, and isolated DC-to-DC converter or brick, which supplies the entire electrical system, exhibits large distribution power losses and low efficiency. With these converters, large bulky cables and connectors are used to overcome demands of high bus currents. The resulting system is susceptible to poor regulation and crosstalk.

A distributed power architecture that uses the intermediate bus to supply several POL buck regulators can deliver their loads locally. This system reduces distribution losses through smaller cables and connectors, which reduce size, weight, and cost. By placing the POL buck regulators close to the load, steady state and dynamic (transient) load regulation is improved, and crosstalk is reduced.

Figure 3 shows how this system can be implemented. In this system, a single POL buck regulator is used to supply up to 10A to a demanding FPGA core. If more power is required, a current- sharing technique may be used. Lower-current POLs are used for the less demanding auxiliary and I/O supplies where load transient and output voltage ripple are still important. The PGOOD function is used to trigger the subsequent regulators if sequencing is required. An inverted clock (SYNC) signal provides frequency synchronization to the subsequent converters. Driving additional converters 180 degrees out-of-phase can reduce the amplitude of input currents, the physical size and the electrical requirements of the input capacitance.

Thermal Management

Figure 4. POL buck regulator efficiency performance for typical output-voltage settings.
As power requirements increase and designs become more complex, heat generated by power loss in electronic components can degrade system performance and reliability. One benefit to using switching regulators is their improved efficiency, which translates directly to improved heat dissipation and reduced temperature generation. Ideally, switching regulators with the highest efficiency are desired where thermal management is important. Figure 4 shows how Peregrine Semiconductor’s PE99155 10A POL buck regulator can be designed to maximize efficiency and improve the thermal dissipation of the device.

Packaging and assembly issues are another concern when managing power dissipation. Smaller packages used with integrated POL buck regulators must provide a short thermal path from the junction of the die to the base of the package. A package with a low thermal resistivity is preferred because the majority of the heat is dissipated through the bottom of the package. The small ceramic package, which has a thin SOS die, has an extremely low thermal resistance of 2.8°C/W junction-tocase. Optimal heat removal and electrical performance is achieved by soldering the bottom of the exposed package paddle to ground.


Rad-hard POL buck regulators with integrated switches provide significant benefits for today’s defense power-management applications. Peregrine’s pa - tent ed UltraCMOS technology enables the integration of analog and digital functions on a single, monolithic radhard die, providing valuable advantages, such as high reliability, and decreased size, weight, and cost. Additionally, key performance factors, such as frequency synchronization, power sequencing, and current-sharing capabilities, provide design flexibility for defense applications as digital system power-management requirements become more demanding.

This article was written by Greg Horvath, Product Applications Engineer, and Anup Singh, High-Reliability Product Manager, Peregrine Semiconductor Corporation (San Diego, CA). For more information, Click Here 

Defense Tech Briefs Magazine

This article first appeared in the June, 2013 issue of Defense Tech Briefs Magazine.

Read more articles from this issue here.

Read more articles from the archives here.