Application Briefs

As wireless standards become more complex, the number of operational modes for these devices increases exponentially. As progression continues to the latest WiFi standard, new modulation schemes, more channels, more bandwidth settings, and additional spatial streams are added. Additionally, characterizing WLAN transceivers is especially challenging when faced with thousands of independent operational gain settings.

A block diagram of a typical WLAN receiver shows how each component has multiple gain stages, resulting in hundreds of thousands of different possible gain settings for a single receiver.
Each component of a WLAN transceiver has multiple gain stages. To develop a high-performance radio in a low-cost CMOS process, the design team at Qualcomm Atheros relies on flexible operation at each stage of the radio structure. Multiple gain settings drive a geometric increase in the number of possible setting combinations as each stage is added, which results in hundreds of thousands of data points for a single operational mode. These hundreds of thousands of data points are only for a single radio transceiver, and the number of permutations continues to increase for MIMO configurations where the system uses multiple antennas. This geometric increase in the number of possible setting combinations poses a significant challenge in preventing test times from increasing as well.

To tackle these test time challenges, Qualcomm Atheros uses the NI PXIe-5644R vector signal transceiver. Because it features an onboard field-programmable gate array (FPGA), Qualcomm Atheros can control the digital interface to the chip simultaneously with the RF signal generator and analyzer included in the vector signal transceiver.

Traditionally, FPGAs have been programmed using the VHSIC hardware description language or Verilog. Many engineers and scientists are either not familiar with these complex languages, or require a tool that gives them faster design productivity at a higher level of abstraction to simplify the process of generating FPGA code. LabVIEW is well suited for FPGA programming because it represents parallelism and data flow, so users who are both experienced and inexperienced in traditional FPGA design can productively apply the power of reconfigurable hardware.

Qualcomm Atheros digitally controls the device under test using LabVIEW to program the FPGA on the NI vector signal transceiver.
Qualcomm Atheros used LabVIEW to program the FPGA on the NI vector signal transceiver for device under test control and data processing. The processing can take place within the instrument itself rather than requiring transfers back and forth over the bus to the controller, resulting in significantly faster test times.

Traditional rack-and-stack measurements are limited to best-estimate gain table selections. In this setup, Qualcomm Atheros determined a final solution through iterative estimations, each of which required a regression of the gain table characterization. This was a slow process that produced approximately 40 meaningful data points per iteration. After switching to the NI vector signal transceiver, the team could perform full gain table sweeps instead of using the iterative approach because of the test time improvements. The team could then characterize the entire range of radio operation in one test sweep per device to acquire all 300,000 data points for better determination of the optimal operational settings empirically. The availability of this data provided a view of the device operation never seen before so the team could explore operational regimes not previously considered.

By synchronizing the timing of digital control directly with the RF front end of the instrument, the team has seen test times improve by more than 20X over the previous PXI solution, and up to 200X over the original solution that used traditional instruments.

This article was written by Doug Johnson of Qualcomm Atheros, San Jose, CA, using National Instruments hardware and software. For more information, Click Here.