Tech Briefs

Cryptographic computer systems are needed for secure communications in military, homeland security, medical, and financial applications.

New architectures have been developed for cryptographic hardware that offer high throughput, algorithm flexibility, radiation hardness, and low power. The asynchronous (clockless) architecture combines a dedicated large-integer processor (LIP), a field programmable gate array (FPGA), and a simple processor. The asynchronous LIP can perform public-key encryption using large keys at a fraction of the runtime energy consumption of synchronous (clocked) systems. The system is made of quasi-independent components that can be commercialized as stand-alone or in different configurations.

The LIP architecture consists of a large array of computing elements communicating by message passing. The architecture mixes granularities in order to match the needs of different cryptographic protocols and the different phases within each protocol. FPGAs are helpful in implementing private-key systems and can be used to configure partially evaluated arithmetic functions for public-key protocols.

The LIP’s public-key cryptographic operations were performed in the Large Integer Datapath (LID), which is optimized for maximum throughput and support of different key sizes. Since each operation requires a very large number of bit operations, a number of arithmetic algorithms must be applied to reduce the number of bit-ops to close to what is achieved by the best-known algorithms.

The LIP architecture enables trading speed for energy over a wide range. Speed is limited only by power and heat-dissipation concerns. Operated at full speed, a “simple” LIP based on a 512-bit array multiplier, could perform 300,000 RSA (public-key) decryptions per second using about 300 watts of power. The low-energy operation of the LIP is practical only with an asynchronous implementation. Unless the LIP is used continuously, clock gating would be necessary for energy efficiency.

This work was done by Alain J. Martin of Situs Logic for the Air Force Research Laboratory. AFRL-0117

This Brief includes a Technical Support Package (TSP).

Asynchronous Architectures for Large-Integer Processors (reference AFRL-0117) is currently available for download from the TSP library.

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