Electronics & Computers

Compact Embedded Computer

Mercury Computer Systems (Chelmsford, MA) has introduced the PowerBlock™ 50 system, a high-performance, ultra-compact embedded computer. The system's modular architecture allows for flexible configurations of multiple processors, delivering well over 100 GFLOPS of processing power in a small, lightweight package. A fully configured PowerBlock 50 weighs less than 10 pounds and measures approximately 4" × 5" × 6". The system is available now as the PowerBlock 50 EDK (Engineering Development Kit), which is a complete software development platform. The EDK includes a PowerBlock 50 system, Linux BSP development environment, and a desktop heat rejection unit (HRU) to support the PowerBlock 50's cooling requirements. The PowerBlock 50 EDK is customizable into configurations that include PowerQUICC™, Virtex™-4, and Intel processors, and SATA storage. Each configuration includes Gigabit Ethernet and RS-232 I/O interfaces.

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Ethernet Protocol Analyzer

Absolute Analysis (Newbury Park, CA) has released a 10Gbps Ethernet protocol analyzer employing a SFP+ (Small Form-Factor Pluggable) interface and support for the 10GBase-LRM (Long Reach Multimode) standard. The 10Gbps SFP+ test solution provides developers with the capability to connect up to 16 ports in a single chassis, simultaneously utilizing both Ethernet and Fiber Channel. These ports are each synchronized to a common clock, allowing users to monitor multiple points in the network and aggregated links, and time correlate trace information for anomalies.

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Magnetic Memory Devices for Embedded Computing

A program of research has been dedicated to the development of magnetic memory devices than can be incorporated into complementary metal oxide/semiconductor (CMOS) integrated circuits, wherein these devices can be made to function as radiation- hard logic elements and as components of small random-access memories. The goal of this development was not to provide for large-scale, bulk memories, but, instead, to provide for latches and flip-flops that can serve as state and data registers for sequential logic and as configuration registers for configurable logic. A major benefit afforded by these devices is the ability to retain the logical state of a subsystem that contains the devices when turning off the power to that subsystem to save energy until operation of the subsystem is required. The subsystem can then be powered up and begin operating within a time of the order of milliseconds.

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Interview with Ray Alderman, Executive Director of VITA

Founded in 1984 to promote VMEbus technology, VITA is a non-profit organization of more than 125 vendor companies who share a common interest in real-time, modular embedded computing systems. In August 2008, VITA's Executive Director, Ray Alderman, agreed to speak with Embedded Technology's editor, Bruce Bennett, about the state of VME technology in 2008, how far it has come in its 30-year history, and where it is likely to go in the future.

Posted in: Articles, Articles, Electronics & Computers, Embedded software, People and personalities
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Modeling System Architecture and Resource Constraints Using Discrete-Event Simulation

Optimizing system resource utilization is a key design objective for system engineers in communications, electronics, and other industries. System resources such as processors, memory, or bandwidth on a communication bus are often shared by various components in the system. To understand the utilization of a shared resource, system engineers must do two things: they must identify constraints on the resource, such as number of processors and memory size, and they must analyze the effect of input traffic or load on the shared resource.

Posted in: Articles, Articles, Electronics & Computers, Computer simulation, Optimization, Architecture
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RapidIO vs. Ethernet A Practical Technical Comparison

Ethernet is currently the incumbent backplane technology across a wide range of storage, wireless, wireline, military, industrial, and other embedded applications as developers move away from proprietary implementations in an effort to reduce development time and cost while increasing performance and functionality. However, as data rates increase, it has become apparent that many high-performance applications exceed the limits of this traditional protocol. Designing an efficient embedded backplane interconnect with excellent performance requires addressing a number of key design challenges, including header efficiency, protocol processing efficiency, effective bandwidth, and quality of service while strictly managing cost. To meet these challenges, many developers are turning to RapidIO® technology as an alternative to Ethernet.

Posted in: Articles, Articles, Electronics & Computers, Architecture, Data exchange, Embedded software, Data management, Technical reference
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Designing Software Radio Systems With FPGAs

Software defined radio technology has been widely adopted for new military and aerospace platforms, government signal intelligence and homeland security systems, and now more extensively in commercial wireless voice and data networks as well. These modern communication systems need to squeeze more channels of traffic into an expensive slice of precious radio spectrum. Military and government requirements for secure communications mandate real-time encryption and decryption schemes that must be increasingly more resistant to interception. In multinational theater of war combat operations, communications systems must selectively ensure certain specific links and reliably deny others.

Posted in: Articles, Articles, Electronics & Computers, Communication protocols, Cryptography, Integrated circuits, Radio equipment, Defense industry
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Front Panel Hardware Considerations For ATCA, AMC, and MicroTCA Telecom Equipment

Acceptance of telecom industry standards for rack-mounted server equipment — in the form of the PCI Industrial Computer Manufacturer’s Group (PICMG) standards — is gaining momentum throughout global market channels. The objectives of those standards are certainly attractive in terms of streamlining economy and efficiency for both carriers and telecom equipment manufacturers across a number of areas. Their aim is to reduce development time and costs, as well as to help reduce the total cost of ownership. They are also intended to offer high levels of modularity and configurability while delivering high levels of service availability (99.999% and greater) and supporting appropriate scalability of system performance and capacity.

Posted in: Application Briefs, Application Briefs, Electronics & Computers, Telecommunications systems, Market research, Standardization
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System-On-Module Standard

MEN Micro Inc. (Ambler, PA) has announced the ESMexpress® System-On-Module Standard, a new computing standard in development to be the ANSIVITA 59 (RSE Rugged System- On-Module Express) standard. In conjunction with the new standard, they have also an - nounced the XM1 featuring the first-generation Intel® Atom® processor (Z530 at 1.6 GHz or Z510 at 1.1 GHz) based on 45-nm technology coupled with 1 GB of soldered DDR2 SDRAM for significantly lower power dissipation, reduction in design costs, and space-saving design flexibility. ESMexpress combines this model with advanced cooling technologies, and the latest serial buses and rugged components to ensure safe, reliable operation in harsh environments found in areas as diverse as the railway, avionics, industrial automation, medical engineering and mobile industries.

ESMexpress provides for extreme resistance against shock and vibration. Eight screws secure the module to the carrier board. In addition, a mechanically robust connector specified for MIL and railway applications supports differential signals with up to 8 GHz, features a stacking height of 5 mm with a minimum tolerance of +/-0.3 mm, is equipped with fixed contacts for power supply, and is specified for an operating temperature range of -55°C to +125°C. The Intel-based XM1 offers a screened temperature range of -40°C to +85°C. The electrical signals are distributed on two 120-pin connectors and are only defined for modern serial buses. For PCI Express there are four single lane ports (4 ×1) and one port that can be configured as 1 ×16, 1 ×8, 2 ×4 or 2 ×1. Other ports include three 1-Gigabit Ethernet (also as 10- Gigabit), eight USB, three SATA, SDVO, LVDS, HD Audio, several utility signals, and a single 12V power supply.

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FPGA Mezzanine Card Module

VMETRO (Houston, TX) has released a FPGA Mezzanine Card (FMC/VITA 57) module. The ADC510, available in air-cooled and conduction- cooled rugged versions, integrates two 12-bit 500MHz A/D chips for use in DSP applications such as signal intelligence (SIGINT), electronic counter measures (ECM), and radar. This design, based on the emerging VITA 57.1 standard, makes it easier for developers to integrate FPGAs into their embedded system designs.

The ADC510 supports two Texas Instruments ADS5463 ADC devices, with each device supporting a sampling rate up to 500 MSPS and providing 12-bits of digital output. The ADC device interfaces are routed to the FMC connector to enable an FPGA on a baseboard to directly control and receive data. There is a choice of sample clock sources for the ADC510 including an onboard source that supports sampling rates of 300, 320, 400, and 500 MSPS as well as the ability to utilize an external sample clock. Input and output triggers are provided to enable multiple ADC510 modules to be synchronized to increase the number of input channels.

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