The fundamental understanding of cerebral systems and associated diseases relies on the electrical recording of single neuron activity. This requires in vivo interfacing with neurons using micrometer-scale electrodes. Traditionally, this challenging task is being performed using: single wire electrodes, probes containing small ensembles of electrodes or, more recently, multi-electrode arrays. These electrode arrangements have the potential to gather signals in three-dimensional space and to provide important laminar information. However, the types of arrays that have been proposed so far are either restricted to sampling in a given plane or have difficulty in collecting data in complex regions, such as those found in highly convoluted cortices. Moreover, state-of-the-art micro-electrode systems are not (yet) suitable for obtaining highly stable signals over extended recording periods. In some cases, the probes are just too bulky to follow cortical motion in chronic applications. Also, the damage inflicted to tissue and the way tissue responds to the presence of a foreign body are presently restrictive to chronic neural recordings. Such a chronic use is, however, highly needed, since it allows the study of changes in population activity at single neuron level and at the interaction level with learning, memory and training.

Proper thermal design of any electronics-based system is key to its long-term reliability. NASA engineering expertise in this area is renowned. The International Space Station (ISS) operates in a temperature environment from 250 degrees F (121 °C), down to a minus 250 degrees F (-157 °C), while maintaining a survivable internal temperature. Yet, in the commercial electronics industry many systems engineers have limited knowledge about thermal design. Furthermore, military and industrial customers with wide temperature range applications, want to save money by using commercially available off-the-shelf (COTS) equipment.

With high-profile data breaches making headlines regularly, organizations are carefully evaluating their options for protecting mobile data. For years, software full disk encryption, (FDE), has been the preferred means of addressing this threat. But widespread adoption has been hampered by the complexity and cost surrounding these software-based FDE deployments.

Software test tools have been traditionally designed with the expectation that the code has been (or is being) designed and developed following a best practice development process. Legacy code turns the ideal process on its head. Although such code is a valuable asset, it is likely to have been developed on an experimental, ad hoc basis by a series of “gurus” — experts who prided themselves on getting things done and in knowing the application itself, but not necessarily expert at complying with modern development thinking and bored with providing complete documentation. That doesn’t sit well with the requirements of standards such as DO-178B.

The computing press is full of discussions about multicore systems, defined here as single-chip computers containing two or more processing cores each connected to a common shared memory (Figure 1).

These devices are being presented as the solution to the performance problems faced by embedded systems, but in fact, multicore may be more of a problem than a solution.

With each new generation of FPGA devices, Xilinx continues to push the performance envelope to match the ever-increasing requirements of target applications. The recent announcement of the Virtex-6 is no exception. More processing power, lower power consumption and updated interface features to match the latest technology I/O requirements are all part of the new devices. While it might be easy to assume that faster, bigger, more powerful is better, it’s important to understand how the latest FPGA innovations actually deliver this higher performance to best match the device to the specific requirements of the application.

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Wireless connectivity is merging with technological advancements in silicon, signaling, mass storage and software to meet the high-performance, ultra-low power requirements for next-generation wireless systems. Embedded form factors, seeking to utilize these developing technologies to the best advantage of system designers, continue to evolve by providing enhanced capabilities while simultaneously reducing form factor footprints. As wireless connectivity becomes increasingly ubiquitous, the volume of embedded systems that utilize wireless is expanding. This perpetuates the demand for higher processing power with minimal power draw and size.